Inverse transform sampling through ray tracing

ABSTRACT

High quality image rendering can be achieved in part by using inverse transform sampling to direct sampling toward regions of greater importance, such as regions with higher brightness values, to reduce noise and improve convergence. Inverse transform sampling can be achieved more efficiently by reformulating as a ray-tracing problem, using tree traversal units that can be accelerated. A geometric mesh can be generated based on a set of cumulative distribution functions (CDFs) for various rows and columns of pixels in a texture, and individual rays can be traced against this mesh, with those rays having a higher probability of intersection at a point with greater importance, such as a higher brightness value. A probability distribution function to be used for importance sampling can be derived by analyzing partial derivatives of the CDF geometry at the intersection location.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present disclosure is a continuation of U.S. patent application Ser.No. 17/458,232, filed Aug. 26, 2021, entitled “INVERSE TRANSFORMSAMPLING THROUGH RAY TRACING,” the entire disclosure of which isincorporated by reference herein for all intents and purposes.

BACKGROUND

As display technology continues to improve, there is a correspondingdesire to improve the quality of content to be rendered on thesedisplays. For content such as gaming or animation, this can involvetechniques such as ray tracing to determine the color values forindividual pixels of rendered image or video content. For real-time raytracers, such as may generate streams of image data for online gaming,performance is important to avoid issues with latency while stillproviding high quality content. Attempts to reduce noise or variancebetween image or video frames are generally constrained by a givenperformance budget, which often results in selection of a less effectivenoise reduction strategy over a strategy that may be more effective butalso comes with higher cost.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments in accordance with the present disclosure will bedescribed with reference to the drawings, in which:

FIGS. 1A and 1B illustrate example images that can be processed,according to at least one embodiment;

FIGS. 2A and 2B illustrate probability and cumulative distributionfunctions that can be determined from image or texture data inaccordance with various embodiments;

FIGS. 3A, 3B, 3C, and 3D illustrate representations of a texture thatcan be utilized for ray tracing-based sampling, according to at leastone embodiment;

FIG. 4 illustrates an example rendering pipeline that can be used torender image content, according to at least one embodiment;

FIG. 5 illustrates a process for determining lighting or shadinginformation for an image, according to at least one embodiment;

FIG. 6 illustrates components of a system for generating and/ortransmitting image data, according to at least one embodiment;

FIG. 7A illustrates inference and/or training logic, according to atleast one embodiment;

FIG. 7B illustrates inference and/or training logic, according to atleast one embodiment;

FIG. 8 illustrates an example data center system, according to at leastone embodiment;

FIG. 9 illustrates a computer system, according to at least oneembodiment;

FIG. 10 illustrates a computer system, according to at least oneembodiment;

FIG. 11 illustrates at least portions of a graphics processor, accordingto one or more embodiments;

FIG. 12 illustrates at least portions of a graphics processor, accordingto one or more embodiments;

FIG. 13 is an example data flow diagram for an advanced computingpipeline, in accordance with at least one embodiment;

FIG. 14 is a system diagram for an example system for training,adapting, instantiating and deploying machine learning models in anadvanced computing pipeline, in accordance with at least one embodiment;and

FIGS. 15A and 15B illustrate a data flow diagram for a process to traina machine learning model, as well as client-server architecture toenhance annotation tools with pre-trained annotation models, inaccordance with at least one embodiment.

DETAILED DESCRIPTION

Approaches in accordance with various embodiments can provide forgeneration of image data. In particular, various embodiments can providefor the efficient generation of high quality images from components suchas textures and assets, where textures can provide a source ofillumination for one or more assets in a scene to be rendered. In orderto make such a lighting or shading process efficient, aspects of theprocess can be mapped to hardware units that can provide forhardware-based acceleration. An approach in accordance with at least oneembodiment can determine one or more cumulative distribution functionsfor a texture, and can construct a geometric representation from thatcumulative distribution, such that one or more rays can be tracedagainst that geometry to perform sampling in a way that supportshardware acceleration. Large emissive textures can be utilized, whichcan increase the detail and overall realism of a scene, providing aneffective source of environmental lighting for a scene. Importancesampling of these large emissive textures can help to reduce an amountof noise in an image that might otherwise be introduced if, for example,these textures were naively sampled, as a majority of incoming radiancemay originate from a small fraction of the texels of a texture, andrandom sampling with equal probability may result in these small,influential texels rarely being sampled.

In at least one embodiment, importance sampling of large emissivetextures can be performed using inverse transform sampling. Whiletraditional inverse transform sampling can be utilized with somesuccess, this sampling performance may be unreliable due to theunpredictable nature of binary search. Moreover, traditional inversetransform sampling does not allow for control over whether, or by howmuch, to prioritize variance reduction or performance. Approaches inaccordance with at least one embodiment can utilize a ray traversalsearch, such as a single hardware-accelerated ray-traversal search overcumulative probability geometry, instead of traditional binary searchesperformed in texture space. The use of a ray traversal search can enablethe leveraging of ray tracing hardware, which can significantly improveperformance of importance sampling. Such importance sampling performanceimprovements have been shown to translate to improved renderingperformance, by up to 70% in one example, while achieving a similarreduction in variance to traditional inverse transform sampling.Moreover, the intersected cumulative probability geometry can bemodified to enable prioritizing performance over variance reduction.

FIG. 1A illustrates an example image 100 to be generated. In thisexample, there are two primary components that make up this image. Abackground texture is used that provides a view of one or morebackground objects for a scene, as well as a foreground object 104 thatrepresents an object such as a character avatar, non-player character,or scene object, in this case a boat. In various embodiments,information useful for lighting or shading of an asset or object will beincluded in a texture. For purposes of simplicity, the term “lighting”shall be used herein to refer generally to determining an amount oflight incident on a surface of an object or asset, or a color valueresulting from such illumination, even though other terms such as“shading” may more commonly be used in specific applications or usecases. In order to make a generated image appear more realistic whendisplayed, a rendering process can determine aspects such as lighting,reflections, shadows, and caustic patterns that may result from one ormore sources of light in a scene. In this example, the backgroundobjects in the example texture can impact an illumination, or coloring,of the boat 104 in the scene. Based on factors such as placement in thescene and brightness of an object, there will be some objects thatimpact the lighting of various objects in this scene more than others.In the present example, if realistically rendered then the sun 102 willprovide a majority of the illumination in the scene, while a sky regionmay provide at least some amount of illumination and the ground or treesmay provide little illumination. If values such as the brightness valuesof individual pixels were analyzed, these brightness values would berepresentative of an amount of illumination provided by various portionsof a given texture. As an example, FIG. 1B illustrates a very lowresolution version 150 of the texture of FIG. 1A, using low resolutionfor simplicity of explanation. The color values of these pixelscorrespond to the relative brightness or other light-determining aspectsof these pixels, which can be referred to as a type of “importance”value for lighting of an object or scene. As illustrated, a pixel 152corresponding generally to a location of the sun in the texture is shownas a brightest pixel, or pixel with greatest importance forillumination. The pixels 154 corresponding to a sky region are not asbright, demonstrating that they will generally contribute less to theoverall lighting of the scene than the sun, and thus have a lowerimportance from a lighting perspective. The pixels 156 corresponding tothe ground or surface region are even less bright, demonstrating thatthey will contribute even less to the lighting of objects in the scene,and are of even lower importance from a lighting perspective.

When rendering a scene, an approach that may generate a highly realisticimage would be to sample the lighting contribution by tracing rays outfrom a screen into a 3D scene. When these traced rays hit objects inthat 3D scene, shadow rays can be traced form those intersectionlocations on 3D objects to another object with an emissive textureapplied. In many instances, artists will construct a sphere thatencloses an entire 3D scene, where an emissive texture is mapped to thatsphere using a latitude/longitude projection. The emissive texturedsphere can then light the scene from all directions. In other scenarios,artists may instead apply emissive textures to 3D objects within ascene. For example, a 3D quadrilateral face might have a “lava” textureapplied, where the lava texture emits orange light. Performing a binarysearch during classical inverse transform sampling identifies pixels inthe background image to trace a ray towards can result in a significantnumber of computations per image or video frame, which may prove toocostly in many situations, particularly for real-time rendering whereimages may need to be generated at a frame rate on the order of 60 Hz,90 Hz, or higher, and where that rendering often needs to be performedusing a client device that may have limited rendering or computingcapacity. Accordingly, approaches in accordance with various embodimentscan instead trace a subset of these rays for each image or frame todetermine lighting, color, and other such values. In many embodiments,this involves sampling a different subset of pixels or rays fordifferent frames, as utilizing the same subset for each frame couldresult in missing contributions from some pixels or overemphasizing thecontributions of other pixels.

When selecting pixels or rays to sample, it can be beneficial toconcentrate that sampling on the pixels or locations that have greaterimpact on the lighting of objects, or that have greater importance froma lighting perspective. Accordingly, approaches in accordance with atleast some embodiments can utilize an approach such as importancesampling. Importance sampling is an approximation approach that can helpto reduce variance in many situations as opposed to traditional acceptor reject sampling.

In at least one embodiment, geometric representations of emissivetextures can be generated based, at least in part, upon probabilitydistributions determined for those textures. As an example, FIG. 2Aillustrate a set of distributions 200 that can be determined in onedimension (1D). An example 1D row 202 of brightness values is utilized.From this distribution, a probability distribution 204 can becalculated. As illustrated, this distribution shows that the highestlighting importance comes from a middle region of the row, with a width(or standard deviation around a mean) corresponding to the relativebrightness of the pixels in that row. A cumulative distribution function206 can be generated that is based upon this probability distributionfunction. As illustrated, this cumulative function when plotted has asteepest slope at locations of highest importance. This property lendsitself to ray tracing-based sampling.

For example, consider the view 250 of these distributions illustrated inFIG. 2B. Due to the relative steepness of the curve at areas ofdifferent brightness or importance, a random ray will have a higherprobability of hitting, or intersecting, a point on that cumulativedistribution curve that corresponds to a point of higher brightness orimportance. As illustrated in this example, a majority (here 60%) of thepixels from which rays can be cast will hit pixels in a region ofhighest importance, such as a sun region. The majority of these rayswill then intersect the curve at locations that correspond to a minority(here 40%) of the pixels, which also correspond to the most importantpixels. Thus, this approach increases a probability of a rayintersecting a pixel with a relatively high brightness or importancevalue.

In order to utilize such an approach for 2D, 3D, 4D, or multi-modalimages, for example, such an approach can be extended beyond onedimensional data. In some embodiments, slices of 3D data can bedetermined to reduce this 3D case to a set of 2D cases. FIGS. 3A and 3Billustrate an example approach that can be used for explanation withrespect to the low resolution texture previously illustrated in FIG. 1B.In this example the brightness values can first be analyzed using aprobability distribution function for each row. For each row, the set ofprobabilities for the individual pixels can sum to one, as part of aconditional distribution. For the rows 302, 304, 306 where thebrightness or importance values were relatively similar, thedistribution function will show similar values for all pixels in a givenrow. For a row 308 with a significant variation in brightness orimportance, such as row that includes one or more pixels correspondingto the sun, the relative importance of a pixel will be high, hererepresented by a white color, while the relatively importance of theother pixels in that row will be low, represented by a dark color. In animportance range that is normalized between 0 and 1, with 1 being ofhighest importance and 0 being of lowest importance, a white pixel mightcorrespond to a value of 1 and a black pixel might correspond to a valueof 0. A similar analysis can be performed for columns of this lowresolution texture based, at least in part, upon values in this row.

Cumulative distribution functions (CDFs) can be determined for thistexture as well, as illustrated in image 330 of FIG. 3B. In thisexample, a cumulative distribution has been determined for each row.Since the values of pixels in rows 302, 304, 306 are substantiallysimilar across the rows, the cumulative distribution will have asubstantially linearly increasing slope from a minimum importance valueto a maximum importance value. For the row 380 with varying brightnessor importance, however, the cumulative function will have a significantchange in slope near the point of highest brightness or importance, orwithin the standard deviation of the mean of the probabilitydistribution curve. As illustrated, there is a much more drastic changein importance values near the region of brightness or highestimportance. In this approach, each row is assigned a probability, suchthat the row probabilities sum to one as part of a marginaldistribution. This marginal CDF can then be inverted, sampling the CDFrandomly to select a row to redirect a sample towards. Using that row, asampling process can invert the corresponding CDF for that row at arandom value to select a column to redirect the sample towards. Invarious embodiments, a user, application, or entity can choose to encodeinverse CDFs geometrically using widths, heights, depths, and/orcorresponding geometry and primitive data.

A benefit of such an approach is illustrated in the perspective viewplot 360 of FIG. 3C. In this view, which is rotated with respect to FIG.3B but still shows the same rows, the importance or brightness value foreach pixel location is represented as a height from 0 to 1 in additionto a color. While this example is shown graphically for purposes ofexplanation, it should be understood that these functions can becomputed mathematically, and such plots or views are not necessary toimplement aspects of various embodiments presented herein. In order toperform a type of importance sampling, a set of random rays can betraced to determine points of intersection with this geometric mesh orrepresentation, and pixels of texture that correspond to those points ofintersection with the mesh can be used to determine lighting for acorresponding image or video frame. In at least some embodiments, thiscan involve tracing a number of rays at random (or otherwise determined,selected, or sampled) locations and determining the points ofintersection. As illustrated in FIG. 3C, the amount of “intersectable”area for a given pixel will correspond to a change in importance at, ornear, that pixel locations, corresponding to a slope of the cumulativedistribution function at that location. As illustrated, a pixel locationcorresponding to the sun in the corresponding texture, or the pixel ofhighest importance, has significantly more intersectable area than theother pixels in this view, such that the pixel with highest importancehas the highest probability of being intersected by a random ray 362. Inthis particular view, the pixel corresponding to the sun, which has thelargest impact on the lighting of objects in this scene, is around 6×more likely to be intersected than any other pixel. Thus, a randomsampling or tracing of rays will have a significantly higher probabilityof resulting in a sampling of this most important pixel. For higherresolution images where there may be many pixels corresponding to alight source such as the sun, this can increase the probability that oneor more of those rays, or potentially many of those rays, will samplesun-related pixels for each frame.

In at least some embodiments, it can be desirable to smooth thisgeometric mesh for at least some embodiments. A smoother mesh canrequire fewer triangles or geometric shapes for representation, whichcan require less time to trace rays against that mesh and test forintersections. One such geometric mesh 390 is illustrated in FIG. 3D. Inthis example, smoothing has been applied to the geometric mesh that cantake into account the values or importance of surrounding pixels. Asillustrated, even after smoothing a traced ray 392 will still have ahighest probability of hitting a location corresponding to a sun-relatedpixel.

FIG. 4 illustrates components of an example rendering pipeline 400 thatcan be utilized to render images in accordance with various embodiments.In this example, an application 402 is running on a central processingunit (CPU) 402, where that application includes instructions that can bestored in system memory 404 and executed by the CPU. This applicationcan be, for example, a video game or animation application or processthat provides data about an image to be rendered. In this example, datafor rendering an image can be provided, via an application programminginterface (API) runtime 406 or other such interface mechanism, to agraphics processing unit (GPU) 410. As mentioned, for at least sometypes of rendering or tasks a GPU can provide improved performancerelative to a CPU, particularly for a large number of small paralleltasks, such as may be utilized for rendering of an image, particularlywhere hardware acceleration can be applied to at least some of thosetasks. Instructions can be stored in GPU memory 412 until they areselected or scheduled for execution. In this example, the data andinstructions can be passed to one or more shaders 414, which may includeone or more vertex shading components 416 for adding effects to objectsin a scene or environment, often a 3D environment, by determining thevertex data for one or more objects in a scene and then performingvarious mathematical operations on that object vertex data. In thisexample, the vertex data is passed to one or more geometry components418, which can perform various tasks such as at least some of thosedescribed herein. In this example, this can include tasks such asperforming model and view transformations, performing vertex shading andillumination, performing data projection, performing clipping or cullingof data based on geometry, and determining an appropriate scene map,among other such tasks. For shading or illumination tasks describedherein that can be based at least in part upon cumulative distributionfunctions, these tasks can be performed within the shaders 414 of one ormore GPU on a single computing device or distributed across multipledevices. After these various geometry-based tasks are performed, theresulting data can be passed to a shading component 420 which canperform tasks such as individual pixel shading in order to generateoutput image data for various pixels. This data can then be cached inone or more buffers 424 in (or external to) GPU memory 422 (which can bethe same as, or separate from, GPU memory 412) until it is time totransmit that information for presentation via at least one display 430or other such mechanism, as may be attached to, or contained within, atleast one computing device or system, which may be a same computingdevice or system as includes the CPU 402 and GPU 410. This process canbe performed for each image to be generated, as may make up a sequenceof video frames to be presented via display 430. As discussed elsewhereherein, display 430 is not limited to a conventional video displaydevice, such as a television, monitor, or touch screen, but can alsoinclude a projector, VR/AR/MR headset, wearable display, holographicdisplay, and the like. As will be discussed in more detail with respectto FIG. 6 , such components may be contained in a client device forwhich the video is to be displayed, a server to transmit the content toa client device, or a third party system that is to generate image dataon behalf of a client or server device, among other such options.

FIG. 5 illustrates an example process 500 for generating an image thatcan be performed in accordance with various embodiments. It should beunderstood that for this and other processes discussed herein, there canbe additional, fewer, or alternative steps performed in similar oralternative orders, or at least partially in parallel, within the scopeof the various embodiments unless otherwise specifically stated.Further, although this process is described with respect to imagegeneration it should be understood that advantages of such an importancesampling approach can be utilized advantageously for other applicationsor uses as well. In this example, at least one texture is received 502that is to be used in lighting one or more assets in an image to berendered. In other embodiments or examples, assets or objects other thantextures may be utilized to provide representations of backgroundobjects, light sources, and other such features of an image to begenerated. In this example, a texture can itself be an image or set ofimage data which can include color, pixel, brightness, or other suchvalues for individual locations in the texture, which may correspond toindividual pixel locations. For individual pixel locations in thistexture, importance values can be determined 504 that correspond atleast to brightness values for these pixels. Other values may be used aswell, as may include color values or texture properties that can be usedto determine an extent to which an object represented by this pixel hasan ability to impact an appearance of another object or pixel containedin this image when presented. As mentioned, pixels in a texture thatcorrespond to the sun may have higher importance values than pixels thatcorrespond to black of the night sky, as they can have a greater impacton the illumination of objects in a scene.

In this example, a set of cumulative distribution functions (CDFs) canbe determined 506 for calculated for the texture based at least in partupon these importance values. In some embodiments, a set of probabilitydistributions can be determined for individual rows, columns, or othersubsets of the texture, and these CDFs can be determined from theseindividual probability distributions. A geometric mesh, or othergeometric representation, can then be generated 508 using this set ofCDFs. This can include, for example, a two- or three-dimensional meshwherein points on the mesh with higher importance values have a higherprobability of intersection with a random ray trace than points withlower importance values. Once generated, a set of random rays can betraced with respect to this geometric mesh, and one or more intersectionpoints (or mesh triangles, etc.) of these rays with this mesh can bedetermined 510. Each intersection point can correspond to a pixellocation on the mesh, as may be determined using a distance over whichthe ray is traced, and that pixel can be used for determining lightinginformation for a current image to be generated. An image can then berendered 512, or otherwise generated, that determines lighting for theasset(s) in the scene using color, brightness, pixel, or other valuesfrom the pixels of the texture corresponding to the intersection points.Such an approach allows for a fast sampling of pixels for a shadingprocess, for example, where the probability of sampling is increased forpixels with higher determined importance for the lighting or shadingprocess. Such an approach can also provide, more generally, formemory-efficient, high-performance, high-quality inverse transformsampling for one-dimensional, two-dimensional, and three-dimensionaldata sets. Inverse transform sampling can be used beneficially for taskssuch as Monte Carlo ray-tracing, as it can be used to redirect samplestowards “important” regions to greatly reduce noise and improveconvergence, such as by redirecting a uniform random distribution tolocations within a grid or set of samples based on a probability of eachof those samples. In at least one embodiment, a PDF to be used for MonteCarlo importance sampling can be derived by analyzing the partialderivatives of the CDF geometry at the intersection location, as thederivative of the CDF is a PDF, as discussed in more detail elsewhereherein.

Various aspects of embodiments discussed above may benefit fromadditional detail, at least as to how these aspects may be implementedfor certain applications or use cases. For example, there may be variousways to represent the geometry for a given texture. For example, theremay be a situation where a user wants to perform inverse transformsampling on a one-dimensional CDF. This CDF can be representedgeometrically as a linear ribbon geometry, where the depth encodes thedomain and the height encodes the range of the CDF function. To invertthis CDF, this process could trace a ray against this height field, suchas with a ray origin being a random height between 0 and 1, and thereturned distance can encode the inverse transformed sample. Since theCDF is the anti-derivative of the PDF, the slope of that height field atthe intersection position can be returned as the probability of thatsample occurring.

As another example, using the same one-dimensional case mentionedearlier, this CDF can be encoded geometrically by creating a flatgeometry, where widths of the ribbon segments encode the inverted CDF.This process can then trace a ray randomly against this geometry, anduse that primitive ID to determine the corresponding sample andprobability. For both of these cases, neighboring primitives can bemerged together to save memory and improve performance by using agradient magnitude measure. However, by representing this data usingprimitives compatible with ray traversal units, the search against thisgeometry can be accelerated, further improving performance. Thesedifferent geometric encoding strategies can be combined together toachieve multi-dimensional inverse transform sampling. As an example, aray origin can be initialized such that one axis is set to a constant,and the other two axes are driven using two random variables. Thedirection of this ray can be set to be orthogonal to the two randomizedaxes, aiming towards a mesh used to represent multiple CDFs.

A representative mesh can be constructed using a series of triangulatedribbons, with one ribbon allocated per row in the grid to be sampled.These ribbons can run along the same axis as the earlier ray. Eachribbon can be subdivided into several segments, with at most one segmentper column, and lifted to match the corresponding row “conditional” CDF.The heights of these ribbons can be made to span the possible range ofvalues of the ray along the second randomized axis, with the firstsegment starting with a height matching the lowest possible randomizedaxis value, and ending with a height matching the maximum possiblerandomized axis value, with in-between segments lifting proportionatelyto their corresponding conditional CDF values. The widths of theseribbons are made to follow the inverse of the single row “marginal” CDF,with more probable rows having wider width ribbons and vice versa, andwhere all ribbons together span the possible range of values of the rayalong the first randomized axis. In this configuration, the earliermentioned ray will hit the mesh at some location once traced.

When the previously-mentioned ray is traced against this mesh, the firstrandomized ray axis can effectively select the row depending on theribbon ID that was intersected, avoiding the first binary search. Thesecond randomized ray axis can cause the ray to lift with the ribbons,causing the intersection distance to grow larger or shorter. This hitdistance effectively selects the column, avoiding the second binarysearch. The probability for the selected row can be found using theribbon ID, and the probability for the selected column can be foundusing the slope of the ribbon along the ray direction axis.

As another multi-dimensional reformulation example, users can constructplanar geometry, where widths and heights of quads spanning bothdimensions encode the inverse conditional and marginal CDFs. Thisapproach differs from the earlier reformulation in that distance is nolonger used to encode the conditional CDF domain. A ray origin cansimilarly be modified randomly to sample this planar geometry, where theintersected primitive and corresponding per-primitive data can be usedto redirect the sample. For three-dimensional importance sampling, theearlier mentioned 2D quads can be substituted for 3D hexahedra, where anepsilon-length ray or hardware-accelerated point query could be used tosample hexahedra, and from there look up relevant per-primitive sampleredirection data required for inverse transform sampling.

For any of these or other such reformulated inversion samplingprocesses, the CDF mesh can be simplified to improve traversalperformance while preserving important CDF features. This can involveanalyzing inflection points of the CDF and selecting a subset of thoseinflection points that are most influential. In at least someembodiments, it may also be beneficial to transform this geometry to arange between 0 to 1 for all dimensions, as in at least some situationsthis has been found to improve sample inversion performance with treetraversal units. Otherwise, proxy geometry with vastly different scalesalong different axes can cause internal nodes to grow in size due tobounds quantization, for example, resulting in unnecessary intersectiontests.

As mentioned previously, when integrating a function ƒ, importancesampling can utilize a modified form of the Monte Carlo estimator, wheresampled values ƒ(X_(i)) are divided by their corresponding probabilitiesof being sampled, as may be given by:

$F_{N} = {\frac{1}{N}{\sum\limits_{i = 1}^{N}\frac{f\left( X_{i} \right)}{p\left( X_{i} \right)}}}$This modified estimator allows for a redirection of samples towards moreinfluential regions, where p(X_(i)) effectively serves as a correctionfactor for that redirection.

To use this modified estimator for texture importance sampling, aprocess can first determine and/or rank how influential each texel (orpixel, etc.) is in a given image, which can be determined in at leastone embodiment by converting the image from linear RGB to grayscaleluminance L. This gives a single scalar value per texel that can be usedto estimate how much light a particular texel will emit. Such a processcan consider texels with high luminance to be more important, and viceversa, by computing a joint probability distribution p(X, Y) from theseluminance values, where here the term “joint” is used to refer to thefact that both X and Y coordinates are used to look up the probabilityof a texel, as may be given by:

${p\left( {X,Y} \right)} = \frac{L\left( {X,Y} \right)}{\Sigma_{i,j}{L\left( {i,j} \right)}}$Once this joint probability distribution is determined, a next step canbe to further break down these probabilities into marginal andconditional probabilities that can be used to importance sample a rowand column respectively.

In order to importance sample a row of interest, the marginalprobability p(Y) can be computed for each row. This marginal probabilitycan describe the overall probability of a row, and can allow forsampling of the rows separately from the columns, typically stored inthe margins of a joint probability table, such as may be given by:

${p(Y)} = {\sum\limits_{x}{p\left( {X,Y} \right)}}$

Then, to importance sample the column within a previously-sampled row,the conditional probability p(X|Y) can be computed for each texel withinthat row. The term “conditional” here refers to this probability beingconditional on another event happening. In this example, it is desiredto compute the probability of sampling an X given that a Y was alreadyselected, as may be given by:

${p\left( {X,Y} \right)} = \frac{p\left( {X,Y} \right)}{p(Y)}$

It can then be appropriate in at least some embodiments to performsample redirection. This can involve randomly selecting from aprobability distribution such that the probability of choosing a samplematches that earlier assigned probability for that sample. Thisimportance sampling process should be efficient in variousimplementations, as a process may take many of these samples in a givenray tracer. This can be performed using a process such as inversetransform sampling, as discussed elsewhere herein, which can transformthese probability distributions to enable an efficient samplingalgorithm. More specifically, in at least some embodiments the previousprobability distribution functions (PDFs) can be transformed intocumulative distribution functions (CDFs). A cumulative distributionfunction evaluated at some location X returns the probability that asample will occur whose probability is less than or equal to X. In thisdescription, PDFs are denoted using a lower case p and CDFs using anupper case P, as may be given by:P(X)=∫₀ ^(X) p(X)dX

Since a CDF can function as a running sum of positive probabilityvalues, these functions will generally only go up in value, and never godown. As a result, a CDF can therefore be inverted. This ability toinvert CDFs can be beneficial for tasks such as importance sampling, asthis inversion process can map a uniform distribution into adistribution where highly influential samples are more likely to besampled, and low influence samples are less likely to be sampled. Inpractice, this inversion can be performed numerically as these PDFs canbe discrete arrays derived from luminance, and do not come from ananalytical, invertible equation. Fortunately, this numerical inversioncan be done using, for example, a fast O(log(n)) binary search, as maybe given by:P(Y)=∫₀ ^(Y) p(Y)dYP(X|Y)=∫₀ ^(X) p(X|Y)dX

In practice, a single marginal CDF P(Y) can be computed and stored,along with a conditional CDF P(X|Y) for each row, and with the originalmarginal, conditional, and joint PDFs discarded to safe memory. Duringsampling, two uniformly random numbers ε₁ and ε₂ can be generated. Fromhere a binary search can be employed to determine the first Y coordinatefrom the marginal CDF where P(Y)≥E₁. Using that Y coordinate, aconditional CDF can be selected for that Y, and a binary searchperformed again to determine the X coordinate, where P(X|Y)≥ε₂. Therecan still be a need to compute the probability of taking this sample, asthat probability can serve as a correction factor. As these CDFs are arunning sum of the original PDFs, the original probability densities inX and Y can be computed by doing a simple subtraction:p(X|Y)=P(X|Y)−P(X−|1|Y) and p(Y)=P(Y)−P(Y−1). From there the joint PDFp(X,Y) can be computed as p(X,Y)=p(X|Y) p(Y).

An inverse transform sampling method presented above has been shown tohave a near optimal run time complexity of O(log(N)+log(M)) where N andM represent texture dimensions. There are ways, however, to furtheroptimize such an approach to enable more samples to be taken at the sameperformance budget, while also improving on memory efficiency. Morespecifically, implementation constants associated with inverse transformsampling may still be relatively high, particularly for real-time andinteractive applications. As mentioned, binary search is not optimal asit employs memory access patterns that prevent prefetching of data thatis likely to be accessed in the next iteration. The row and columnaccesses also depend on random numbers, making these accessesincoherent. To further improve performance and memory efficiency,various techniques presented herein can reduce the size of theseimplementation constants by simplifying the CDFs, while also using arepresentation compatible with ray tracing hardware to improve searchperformance.

Within a CDF, many neighboring probabilities may be similar in value.For example, if a texture contains a smooth gradient for the sky,luminance between neighboring pixels will be similar, and as a result,neighboring probabilities will also be similar. The similarity ofneighboring pixels can then be ranked based, at least in part, upon acloseness of their corresponding probabilities. Using that similaritymeasure, merging highly similar pixels can be prioritized, and attemptscan be made to avoid merging neighboring pixels with very differentprobabilities. Structurally, such a similarity measure allows for atrade-off between importance sampling accuracy on one hand, and datalocality on the other. In practice, such merging may not always bestraightforward. By merging neighboring values together, the CDFs gofrom being structured to unstructured, and it may be somewhat difficultto efficiently search through this unstructured data. For one suchstrategy, the CDFs can be interpreted geometrically as height fields.For each address in a CDF array, the associated probabilities can beinterpreted as “heights” ranging from 0 to 1. From this, a geometricmesh can be constructed to represent this height field using linearribbon segments.

Using such an unstructured, geometric reformulation, a search used forinverse transform sampling can be implemented by tracing one or morerays. To sample a CDF geometry, a uniform random number ξ∈(0, 1) can begenerated, but rather than searching for that random number using binarysearch, that random number can be used to control the height of a givenray. That ray can be traced towards a CDF height field, where traversalis used to facilitate the search, as may be given by:r=o+{right arrow over (dt)}o=(0,ε,0){right arrow over (d)}=(1,0,0)

By randomizing they offset of the origin and aiming the ray towards thex axis, the ray can be traced towards the positive incline of the heightfield such that the intersection distance t represents the invertedx-coordinate.

To compute the corresponding sample probability “correction factor” fora Monte Carlo estimator, the derivative of the CDF can be computed atthe sample location, since the derivative of the CDF is the PDF to besampled. Since the height field geometry consists of linear segments,this derivative can be determined by computing the slope of the hitlinear segment. Up until this point, it may have been necessary to tracea ray to facilitate the first search over the marginal CDF P(Y),followed by a second ray to search over the conditional CDF P(X|Y).However, with a few modifications it is possible to search over bothCDFs simultaneously using just one ray.

Instead of representing each CDF geometry as separate ribbon geometry,the third dimension available can be leveraged, along with the hit grouprecords associated with the ribbons, to simultaneously search over themarginal and conditional distributions. As mentioned previously, eachconditional CDF can be represented using simplified ribbon geometry,where the height of the ribbon (e.g., Y in this example) can be used toencode the probability for the column of a given row (e.g., X in thisexample). In at least one embodiment, the inverse of the marginal CDFcan be encoded by altering the thickness and placement of those ribbonsalong the third dimension (e.g., Z in this example), storing thecorresponding “projected” row identifier (ID) and row probability in theribbon hit group record that can be obtained from a closest hit program.

By representing the marginal probabilities using ribbon widths andplacing these ribbons side by side, the marginal CDF heights can beprojected onto the Z axis, effectively encoding the inverse of themarginal CDF. To recover the “projected” address for each marginal CDFsegment, the hit record data corresponding to the hit geometry can bedetermined. Rows that have a marginal probability of 0, indicating thatthe luminance of this row is zero, would obtain zero thickness and thuscannot be hit by rays at all. Conversely, rows that have a high marginalprobability have very wide thickness, making those ribbons more likelyto be hit.

When tracing rays against this combined geometry, the direction of theray can be oriented towards the positive incline of the CDF, {rightarrow over (d)}=(1,0,0), but the origin of the ray can be set to o=(0,ε₁, ε₂), where ε₂ is the random number used to sample the marginaldistribution, and ε₁ is the random number to sample the conditional CDF.From this ray, the sampled y-coordinate can be obtained from themarginal distribution through the row ID associated with the ribbon thatwas hit, followed by the x-coordinate as before through returned hitdistance t.

In at least some embodiments, it can be important while simplifying theconditional and marginal CDFs to preserve variance reduction while alsoreducing implementation constants. Rather than merging neighboringprobabilities together at a local scale, approaches in accordance withvarious embodiments can instead collect a subset of texels at a globalscale that are considered to be of at least a minimum importance. Theseimportant texels can be referred to as control points, as these controlpoints can be used to generate the CDF geometry. A control point can beconstructed for each texel in a given texture, inserting those controlpoints into a list. For each control point, the value of the conditionalCDF at that coordinate can be stored, as well as the first and secondorder partial derivatives of the conditional CDF with respect to X, thedirection of the rows. This array of control points can then be sortedin descending order by their second-order derivatives. Sorting by thesecond-order derivative enables highly influential, “spiky” controlpoints to appear earlier in the list. Control points with smallersecond-order derivative values will appear later in the list, indicatingthat the neighboring texels of these control points are at leastsomewhat similar, and that these control points can be discarded tosimplify the geometric representation. This sorted list can betruncated, such that all but N control points are discarded.

These resulting control points represent row-wise CDFs, with a lowestvalue per CDF of 0 and a highest value of 1. By discarding controlpoints globally, it is possible to result in row CDFs that have nocontrol points associated with them. To address this possibility, the xcoordinate for all control points can first be incremented by 1, makingthese control points vertex-centered at the ends of the texel gridinstead of cell-centered. Next, it can be enforced that each row isrepresented by inserting control points at x=0 with a probability ofP(0|Y)=0, and inserting control points at x=n, if they do not alreadyexist, with a function value of P(n|Y)=1. After sorting and truncatingthis list of control points by their second order partial derivatives,these control points can be re-sorted, first by their x-coordinate, andthen by their y-coordinate, with the latter sort being a stable sort toretain the order in x. These operations can effectively produce a listof unstructured CDFs sorted by row, with each row being represented withat least two control points.

Such a process can result in CDFs that are simplified to a point wherethe control points can be used to generate a geometric representation,such as a geometric mesh. Rays can be traced against this geometry, withtraversal performance improved by using hardware-accelerated traversal,such as is made available using real-time ray tracing acceleration, suchas through RT cores from NVIDIA Corporation as part of their RTX raytracing technology. A ray tracing core in at least some implementationsis a tree-traversal unit that can perform a fast and efficient boundingvolume hierarchy (BVH) traversal in, for example, three dimensions. ABVH can be constructed over 3D triangles of a ribbon, instead of a 2Dline, for use with the ray tracing hardware. For each unstructured CDFrow, ribbon geometry can be generated as described herein such thatconsecutive CDF control points in a row are connected by triangulatedplanar quads. As mentioned previously, the thickness and placement ofthese ribbons in the third dimension can be adjusted in a row-by-rowfashion using corresponding per-row marginal CDF values.

Various additional optimizations can be utilized as well. For example,the dimensions of the CDF geometry can be normalized, as this may leadto more consistently-sized bounding boxes and greatly improved traversalperformance, such as by 45-50% on data sets used for testing. Correctionfor this normalization scale can be performed after sampling. Finally,if neighboring rows are detected that contain only two control pointseach, performance can be further improved, such as by 20-30% on thesedata sets, by merging these neighboring rows together. As a result, oneribbon can span several rows. Rows spanned by a ribbon through the hitgroup record of the ribbon geometry can be uploaded with trianglebarycentrics used to determine which row within the ribbon that raysampled.

As discussed, various approaches presented herein are lightweight enoughto execute on a client device, such as a personal computer or gamingconsole, in real time. Such processing can be performed on content thatis generated on that client device or received from an external source,such as streaming content received over at least one network. The sourcecan be any appropriate source, such as a game host, streaming mediaprovider, third party content provider, or other client device, amongother such options. In some instances, the processing and/or renderingof this content may be performed by one of these other devices, systems,or entities, then provided to the client device (or another suchrecipient) for presentation or another such use.

As an example, FIG. 6 illustrates an example network configuration 600that can be used to provide, generate, modify, encode, and/or transmitcontent. In at least one embodiment, a client device 602 can generate orreceive content for a session using components of a content application604 on client device 602 and data stored locally on that client device.In at least one embodiment, a content application 624 (e.g., an imagegeneration or editing application) executing on content server 620(e.g., a cloud server or edge server) may initiate a session associatedwith at least client device 602, as may utilize a session manager anduser data stored in a user database 634, and can cause content 632 to bedetermined by a content manager 626. An image content application 630may obtain image, asset, and/or texture data for a scene or environmentand work with a rendering engine 628 or other such component to generatean image-based representation of a scene or environment. At least aportion of that content may be transmitted to client device 602 using anappropriate transmission manager 622 to send by download, streaming, oranother such transmission channel. An encoder may be used to encodeand/or compress at least some of this data before transmitting to theclient device 602. In at least one embodiment, content 632 can includevideo or image data for a scene. In at least one embodiment, clientdevice 602 receiving such content can provide this content to acorresponding content application 604, which may also or alternativelyinclude a graphical user interface 610, rendering engine 612, or imagegeneration application 614 or process for generating, modifying, orpresenting image data received to, or generated on, the client device602. A decoder may also be used to decode data received over thenetwork(s) 640 for presentation via client device 602, such as image orvideo content through a display 606 and audio, such as sounds and music,through at least one audio playback device 608, such as speakers orheadphones. In at least one embodiment, at least some of this contentmay already be stored on, rendered on, or accessible to client device602 such that transmission over network 640 is not required for at leastthat portion of content, such as where that content may have beenpreviously downloaded or stored locally on a hard drive or optical disk.In at least one embodiment, a transmission mechanism such as datastreaming can be used to transfer this content from server 620, orcontent database 634, to client device 602. In at least one embodiment,at least a portion of this content can be obtained or streamed fromanother source, such as a third party content service 660 that may alsoinclude a content application 662 for generating or providing content.In at least one embodiment, portions of this functionality can beperformed using multiple computing devices, or multiple processorswithin one or more computing devices, such as may include a combinationof CPUs and GPUs.

In this example, these client devices can include any appropriatecomputing devices, as may include a desktop computer, notebook computer,set-top box, streaming device, gaming console, smartphone, tabletcomputer, VR headset, AR goggles, wearable computer, or a smarttelevision. Each client device can submit a request across at least onewired or wireless network, as may include the Internet, an Ethernet, alocal area network (LAN), or a cellular network, among other suchoptions. In this example, these requests can be submitted to an addressassociated with a cloud provider, who may operate or control one or moreelectronic resources in a cloud provider environment, such as mayinclude a data center or server farm. In at least one embodiment, therequest may be received or processed by at least one edge server, thatsits on a network edge and is outside at least one security layerassociated with the cloud provider environment. In this way, latency canbe reduced by enabling the client devices to interact with servers thatare in closer proximity, while also improving security of resources inthe cloud provider environment.

In at least one embodiment, such a system can be used for performinggraphical rendering operations. In other embodiments, such a system canbe used for other purposes, such as for providing image or video contentto test or validate autonomous machine applications, or for performingdeep learning operations. In at least one embodiment, such a system canbe implemented using an edge device, or may incorporate one or moreVirtual Machines (VMs). In at least one embodiment, such a system can beimplemented at least partially in a data center or at least partiallyusing cloud computing resources.

Inference and Training Logic

FIG. 7A illustrates inference and/or training logic 715 used to performinferencing and/or training operations associated with one or moreembodiments. Details regarding inference and/or training logic 715 areprovided below in conjunction with FIGS. 7A and/or 7B.

In at least one embodiment, inference and/or training logic 715 mayinclude, without limitation, code and/or data storage 701 to storeforward and/or output weight and/or input/output data, and/or otherparameters to configure neurons or layers of a neural network trainedand/or used for inferencing in aspects of one or more embodiments. In atleast one embodiment, training logic 715 may include, or be coupled tocode and/or data storage 701 to store graph code or other software tocontrol timing and/or order, in which weight and/or other parameterinformation is to be loaded to configure, logic, including integerand/or floating point units (collectively, arithmetic logic units(ALUs). In at least one embodiment, code, such as graph code, loadsweight or other parameter information into processor ALUs based on anarchitecture of a neural network to which the code corresponds. In atleast one embodiment, code and/or data storage 701 stores weightparameters and/or input/output data of each layer of a neural networktrained or used in conjunction with one or more embodiments duringforward propagation of input/output data and/or weight parameters duringtraining and/or inferencing using aspects of one or more embodiments. Inat least one embodiment, any portion of code and/or data storage 701 maybe included with other on-chip or off-chip data storage, including aprocessor's L1, L2, or L3 cache or system memory.

In at least one embodiment, any portion of code and/or data storage 701may be internal or external to one or more processors or other hardwarelogic devices or circuits. In at least one embodiment, code and/or codeand/or data storage 701 may be cache memory, dynamic randomlyaddressable memory (“DRAM”), static randomly addressable memory(“SRAM”), non-volatile memory (e.g., Flash memory), or other storage. Inat least one embodiment, choice of whether code and/or code and/or datastorage 701 is internal or external to a processor, for example, orcomprised of DRAM, SRAM, Flash or some other storage type may depend onavailable storage on-chip versus off-chip, latency requirements oftraining and/or inferencing functions being performed, batch size ofdata used in inferencing and/or training of a neural network, or somecombination of these factors.

In at least one embodiment, inference and/or training logic 715 mayinclude, without limitation, a code and/or data storage 705 to storebackward and/or output weight and/or input/output data corresponding toneurons or layers of a neural network trained and/or used forinferencing in aspects of one or more embodiments. In at least oneembodiment, code and/or data storage 705 stores weight parameters and/orinput/output data of each layer of a neural network trained or used inconjunction with one or more embodiments during backward propagation ofinput/output data and/or weight parameters during training and/orinferencing using aspects of one or more embodiments. In at least oneembodiment, training logic 715 may include, or be coupled to code and/ordata storage 705 to store graph code or other software to control timingand/or order, in which weight and/or other parameter information is tobe loaded to configure, logic, including integer and/or floating pointunits (collectively, arithmetic logic units (ALUs). In at least oneembodiment, code, such as graph code, loads weight or other parameterinformation into processor ALUs based on an architecture of a neuralnetwork to which the code corresponds. In at least one embodiment, anyportion of code and/or data storage 705 may be included with otheron-chip or off-chip data storage, including a processor's L1, L2, or L3cache or system memory. In at least one embodiment, any portion of codeand/or data storage 705 may be internal or external to on one or moreprocessors or other hardware logic devices or circuits. In at least oneembodiment, code and/or data storage 705 may be cache memory, DRAM,SRAM, non-volatile memory (e.g., Flash memory), or other storage. In atleast one embodiment, choice of whether code and/or data storage 705 isinternal or external to a processor, for example, or comprised of DRAM,SRAM, Flash or some other storage type may depend on available storageon-chip versus off-chip, latency requirements of training and/orinferencing functions being performed, batch size of data used ininferencing and/or training of a neural network, or some combination ofthese factors.

In at least one embodiment, code and/or data storage 701 and code and/ordata storage 705 may be separate storage structures. In at least oneembodiment, code and/or data storage 701 and code and/or data storage705 may be same storage structure. In at least one embodiment, codeand/or data storage 701 and code and/or data storage 705 may bepartially same storage structure and partially separate storagestructures. In at least one embodiment, any portion of code and/or datastorage 701 and code and/or data storage 705 may be included with otheron-chip or off-chip data storage, including a processor's L1, L2, or L3cache or system memory.

In at least one embodiment, inference and/or training logic 715 mayinclude, without limitation, one or more arithmetic logic unit(s)(“ALU(s)”) 710, including integer and/or floating point units, toperform logical and/or mathematical operations based, at least in parton, or indicated by, training and/or inference code (e.g., graph code),a result of which may produce activations (e.g., output values fromlayers or neurons within a neural network) stored in an activationstorage 720 that are functions of input/output and/or weight parameterdata stored in code and/or data storage 701 and/or code and/or datastorage 705. In at least one embodiment, activations stored inactivation storage 720 are generated according to linear algebraic andor matrix-based mathematics performed by ALU(s) 710 in response toperforming instructions or other code, wherein weight values stored incode and/or data storage 705 and/or code and/or data storage 701 areused as operands along with other values, such as bias values, gradientinformation, momentum values, or other parameters or hyperparameters,any or all of which may be stored in code and/or data storage 705 orcode and/or data storage 701 or another storage on or off-chip.

In at least one embodiment, ALU(s) 710 are included within one or moreprocessors or other hardware logic devices or circuits, whereas inanother embodiment, ALU(s) 710 may be external to a processor or otherhardware logic device or circuit that uses them (e.g., a co-processor).In at least one embodiment, ALUs 710 may be included within aprocessor's execution units or otherwise within a bank of ALUsaccessible by a processor's execution units either within same processoror distributed between different processors of different types (e.g.,central processing units, graphics processing units, fixed functionunits, etc.). In at least one embodiment, code and/or data storage 701,code and/or data storage 705, and activation storage 720 may be on sameprocessor or other hardware logic device or circuit, whereas in anotherembodiment, they may be in different processors or other hardware logicdevices or circuits, or some combination of same and differentprocessors or other hardware logic devices or circuits. In at least oneembodiment, any portion of activation storage 720 may be included withother on-chip or off-chip data storage, including a processor's L1, L2,or L3 cache or system memory. Furthermore, inferencing and/or trainingcode may be stored with other code accessible to a processor or otherhardware logic or circuit and fetched and/or processed using aprocessor's fetch, decode, scheduling, execution, retirement and/orother logical circuits.

In at least one embodiment, activation storage 720 may be cache memory,DRAM, SRAM, non-volatile memory (e.g., Flash memory), or other storage.In at least one embodiment, activation storage 720 may be completely orpartially within or external to one or more processors or other logicalcircuits. In at least one embodiment, choice of whether activationstorage 720 is internal or external to a processor, for example, orcomprised of DRAM, SRAM, Flash or some other storage type may depend onavailable storage on-chip versus off-chip, latency requirements oftraining and/or inferencing functions being performed, batch size ofdata used in inferencing and/or training of a neural network, or somecombination of these factors. In at least one embodiment, inferenceand/or training logic 715 illustrated in FIG. 7 a may be used inconjunction with an application-specific integrated circuit (“ASIC”),such as Tensorflow® Processing Unit from Google, an inference processingunit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processorfrom Intel Corp. In at least one embodiment, inference and/or traininglogic 715 illustrated in FIG. 7 a may be used in conjunction withcentral processing unit (“CPU”) hardware, graphics processing unit(“GPU”) hardware or other hardware, such as field programmable gatearrays (“FPGAs”).

FIG. 7 b illustrates inference and/or training logic 715, according toat least one or more embodiments. In at least one embodiment, inferenceand/or training logic 715 may include, without limitation, hardwarelogic in which computational resources are dedicated or otherwiseexclusively used in conjunction with weight values or other informationcorresponding to one or more layers of neurons within a neural network.In at least one embodiment, inference and/or training logic 715illustrated in FIG. 7 b may be used in conjunction with anapplication-specific integrated circuit (ASIC), such as Tensorflow®Processing Unit from Google, an inference processing unit (IPU) fromGraphcore™, or a Nervana® (e.g., “Lake Crest”) processor from IntelCorp. In at least one embodiment, inference and/or training logic 715illustrated in FIG. 7 b may be used in conjunction with centralprocessing unit (CPU) hardware, graphics processing unit (GPU) hardwareor other hardware, such as field programmable gate arrays (FPGAs). In atleast one embodiment, inference and/or training logic 715 includes,without limitation, code and/or data storage 701 and code and/or datastorage 705, which may be used to store code (e.g., graph code), weightvalues and/or other information, including bias values, gradientinformation, momentum values, and/or other parameter or hyperparameterinformation. In at least one embodiment illustrated in FIG. 7 b , eachof code and/or data storage 701 and code and/or data storage 705 isassociated with a dedicated computational resource, such ascomputational hardware 702 and computational hardware 706, respectively.In at least one embodiment, each of computational hardware 702 andcomputational hardware 706 comprises one or more ALUs that performmathematical functions, such as linear algebraic functions, only oninformation stored in code and/or data storage 701 and code and/or datastorage 705, respectively, result of which is stored in activationstorage 720.

In at least one embodiment, each of code and/or data storage 701 and 705and corresponding computational hardware 702 and 706, respectively,correspond to different layers of a neural network, such that resultingactivation from one “storage/computational pair 701/702” of code and/ordata storage 701 and computational hardware 702 is provided as an inputto “storage/computational pair 705/706” of code and/or data storage 705and computational hardware 706, in order to mirror conceptualorganization of a neural network. In at least one embodiment, each ofstorage/computational pairs 701/702 and 705/706 may correspond to morethan one neural network layer. In at least one embodiment, additionalstorage/computation pairs (not shown) subsequent to or in parallel withstorage computation pairs 701/702 and 705/706 may be included ininference and/or training logic 715.

Data Center

FIG. 8 illustrates an example data center 800, in which at least oneembodiment may be used. In at least one embodiment, data center 800includes a data center infrastructure layer 810, a framework layer 820,a software layer 830, and an application layer 840.

In at least one embodiment, as shown in FIG. 8 , data centerinfrastructure layer 810 may include a resource orchestrator 812,grouped computing resources 814, and node computing resources (“nodeC.R.s”) 816(1)-816(N), where “N” represents any whole, positive integer.In at least one embodiment, node C.R.s 816(1)-816(N) may include, butare not limited to, any number of central processing units (“CPUs”) orother processors (including accelerators, field programmable gate arrays(FPGAs), graphics processors, etc.), memory devices (e.g., dynamicread-only memory), storage devices (e.g., solid state or disk drives),network input/output (“NW I/O”) devices, network switches, virtualmachines (“VMs”), power modules, and cooling modules, etc. In at leastone embodiment, one or more node C.R.s from among node C.R.s816(1)-816(N) may be a server having one or more of above-mentionedcomputing resources.

In at least one embodiment, grouped computing resources 814 may includeseparate groupings of node C.R.s housed within one or more racks (notshown), or many racks housed in data centers at various geographicallocations (also not shown). Separate groupings of node C.R.s withingrouped computing resources 814 may include grouped compute, network,memory or storage resources that may be configured or allocated tosupport one or more workloads. In at least one embodiment, several nodeC.R.s including CPUs or processors may grouped within one or more racksto provide compute resources to support one or more workloads. In atleast one embodiment, one or more racks may also include any number ofpower modules, cooling modules, and network switches, in anycombination.

In at least one embodiment, resource orchestrator 812 may configure orotherwise control one or more node C.R.s 816(1)-816(N) and/or groupedcomputing resources 814. In at least one embodiment, resourceorchestrator 812 may include a software design infrastructure (“SDI”)management entity for data center 800. In at least one embodiment,resource orchestrator may include hardware, software or some combinationthereof.

In at least one embodiment, as shown in FIG. 8 , framework layer 820includes a job scheduler 822, a configuration manager 824, a resourcemanager 826 and a distributed file system 828. In at least oneembodiment, framework layer 820 may include a framework to supportsoftware 832 of software layer 830 and/or one or more application(s) 842of application layer 840. In at least one embodiment, software 832 orapplication(s) 842 may respectively include web-based service softwareor applications, such as those provided by Amazon Web Services, GoogleCloud and Microsoft Azure. In at least one embodiment, framework layer820 may be, but is not limited to, a type of free and open-sourcesoftware web application framework such as Apache Spark™ (hereinafter“Spark”) that may utilize distributed file system 828 for large-scaledata processing (e.g., “big data”). In at least one embodiment, jobscheduler 822 may include a Spark driver to facilitate scheduling ofworkloads supported by various layers of data center 800. In at leastone embodiment, configuration manager 824 may be capable of configuringdifferent layers such as software layer 830 and framework layer 820including Spark and distributed file system 828 for supportinglarge-scale data processing. In at least one embodiment, resourcemanager 826 may be capable of managing clustered or grouped computingresources mapped to or allocated for support of distributed file system828 and job scheduler 822. In at least one embodiment, clustered orgrouped computing resources may include grouped computing resource 814at data center infrastructure layer 810. In at least one embodiment,resource manager 826 may coordinate with resource orchestrator 812 tomanage these mapped or allocated computing resources.

In at least one embodiment, software 832 included in software layer 830may include software used by at least portions of node C.R.s816(1)-816(N), grouped computing resources 814, and/or distributed filesystem 828 of framework layer 820. The one or more types of software mayinclude, but are not limited to, Internet web page search software,e-mail virus scan software, database software, and streaming videocontent software.

In at least one embodiment, application(s) 842 included in applicationlayer 840 may include one or more types of applications used by at leastportions of node C.R.s 816(1)-816(N), grouped computing resources 814,and/or distributed file system 828 of framework layer 820. One or moretypes of applications may include, but are not limited to, any number ofa genomics application, a cognitive compute, and a machine learningapplication, including training or inferencing software, machinelearning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.) orother machine learning applications used in conjunction with one or moreembodiments.

In at least one embodiment, any of configuration manager 824, resourcemanager 826, and resource orchestrator 812 may implement any number andtype of self-modifying actions based on any amount and type of dataacquired in any technically feasible fashion. In at least oneembodiment, self-modifying actions may relieve a data center operator ofdata center 800 from making possibly bad configuration decisions andpossibly avoiding underutilized and/or poor performing portions of adata center.

In at least one embodiment, data center 800 may include tools, services,software or other resources to train one or more machine learning modelsor predict or infer information using one or more machine learningmodels according to one or more embodiments described herein. Forexample, in at least one embodiment, a machine learning model may betrained by calculating weight parameters according to a neural networkarchitecture using software and computing resources described above withrespect to data center 800. In at least one embodiment, trained machinelearning models corresponding to one or more neural networks may be usedto infer or predict information using resources described above withrespect to data center 800 by using weight parameters calculated throughone or more training techniques described herein.

In at least one embodiment, data center may use CPUs,application-specific integrated circuits (ASICs), GPUs, FPGAs, or otherhardware to perform training and/or inferencing using above-describedresources. Moreover, one or more software and/or hardware resourcesdescribed above may be configured as a service to allow users to trainor performing inferencing of information, such as image recognition,speech recognition, or other artificial intelligence services.

Inference and/or training logic 715 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 715 are provided belowin conjunction with FIGS. 7A and/or 7B. In at least one embodiment,inference and/or training logic 715 may be used in system FIG. 8 forinferencing or predicting operations based, at least in part, on weightparameters calculated using neural network training operations, neuralnetwork functions and/or architectures, or neural network use casesdescribed herein.

Such components can be used to render images using ray tracing-basedimportance sampling, which can be accelerated through hardware.

Computer Systems

FIG. 9 is a block diagram illustrating an exemplary computer system,which may be a system with interconnected devices and components, asystem-on-a-chip (SOC) or some combination thereof 900 formed with aprocessor that may include execution units to execute an instruction,according to at least one embodiment. In at least one embodiment,computer system 900 may include, without limitation, a component, suchas a processor 902 to employ execution units including logic to performalgorithms for process data, in accordance with present disclosure, suchas in embodiment described herein. In at least one embodiment, computersystem 900 may include processors, such as PENTIUM® Processor family,Xeon™, Itanium®, XScale™ and/or StrongARM™, Intel® Core™, or Intel®Nervana™ microprocessors available from Intel Corporation of SantaClara, Calif., although other systems (including PCs having othermicroprocessors, engineering workstations, set-top boxes and like) mayalso be used. In at least one embodiment, computer system 900 mayexecute a version of WINDOWS' operating system available from MicrosoftCorporation of Redmond, Wash., although other operating systems (UNIXand Linux for example), embedded software, and/or graphical userinterfaces, may also be used.

Embodiments may be used in other devices such as handheld devices andembedded applications. Some examples of handheld devices includecellular phones, Internet Protocol devices, digital cameras, personaldigital assistants (“PDAs”), and handheld PCs. In at least oneembodiment, embedded applications may include a microcontroller, adigital signal processor (“DSP”), system on a chip, network computers(“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”)switches, or any other system that may perform one or more instructionsin accordance with at least one embodiment.

In at least one embodiment, computer system 900 may include, withoutlimitation, processor 902 that may include, without limitation, one ormore execution units 908 to perform machine learning model trainingand/or inferencing according to techniques described herein. In at leastone embodiment, computer system 900 is a single processor desktop orserver system, but in another embodiment computer system 900 may be amultiprocessor system. In at least one embodiment, processor 902 mayinclude, without limitation, a complex instruction set computer (“CISC”)microprocessor, a reduced instruction set computing (“RISC”)microprocessor, a very long instruction word (“VLIW”) microprocessor, aprocessor implementing a combination of instruction sets, or any otherprocessor device, such as a digital signal processor, for example. In atleast one embodiment, processor 902 may be coupled to a processor bus910 that may transmit data signals between processor 902 and othercomponents in computer system 900.

In at least one embodiment, processor 902 may include, withoutlimitation, a Level 1 (“L1”) internal cache memory (“cache”) 904. In atleast one embodiment, processor 902 may have a single internal cache ormultiple levels of internal cache. In at least one embodiment, cachememory may reside external to processor 902. Other embodiments may alsoinclude a combination of both internal and external caches depending onparticular implementation and needs. In at least one embodiment,register file 906 may store different types of data in various registersincluding, without limitation, integer registers, floating pointregisters, status registers, and instruction pointer register.

In at least one embodiment, execution unit 908, including, withoutlimitation, logic to perform integer and floating point operations, alsoresides in processor 902. In at least one embodiment, processor 902 mayalso include a microcode (“ucode”) read only memory (“ROM”) that storesmicrocode for certain macro instructions. In at least one embodiment,execution unit 908 may include logic to handle a packed instruction set909. In at least one embodiment, by including packed instruction set 909in an instruction set of a general-purpose processor 902, along withassociated circuitry to execute instructions, operations used by manymultimedia applications may be performed using packed data in ageneral-purpose processor 902. In one or more embodiments, manymultimedia applications may be accelerated and executed more efficientlyby using full width of a processor's data bus for performing operationson packed data, which may eliminate need to transfer smaller units ofdata across processor's data bus to perform one or more operations onedata element at a time.

In at least one embodiment, execution unit 908 may also be used inmicrocontrollers, embedded processors, graphics devices, DSPs, and othertypes of logic circuits. In at least one embodiment, computer system 900may include, without limitation, a memory 920. In at least oneembodiment, memory 920 may be implemented as a Dynamic Random AccessMemory (“DRAM”) device, a Static Random Access Memory (“SRAM”) device,flash memory device, or other memory device. In at least one embodiment,memory 920 may store instruction(s) 919 and/or data 921 represented bydata signals that may be executed by processor 902.

In at least one embodiment, system logic chip may be coupled toprocessor bus 910 and memory 920. In at least one embodiment, systemlogic chip may include, without limitation, a memory controller hub(“MCH”) 916, and processor 902 may communicate with MCH 916 viaprocessor bus 910. In at least one embodiment, MCH 916 may provide ahigh bandwidth memory path 918 to memory 920 for instruction and datastorage and for storage of graphics commands, data and textures. In atleast one embodiment, MCH 916 may direct data signals between processor902, memory 920, and other components in computer system 900 and tobridge data signals between processor bus 910, memory 920, and a systemI/O 922. In at least one embodiment, system logic chip may provide agraphics port for coupling to a graphics controller. In at least oneembodiment, MCH 916 may be coupled to memory 920 through a highbandwidth memory path 918 and graphics/video card 912 may be coupled toMCH 916 through an Accelerated Graphics Port (“AGP”) interconnect 914.

In at least one embodiment, computer system 900 may use system I/O 922that is a proprietary hub interface bus to couple MCH 916 to I/Ocontroller hub (“ICH”) 930. In at least one embodiment, ICH 930 mayprovide direct connections to some I/O devices via a local I/O bus. Inat least one embodiment, local I/O bus may include, without limitation,a high-speed I/O bus for connecting peripherals to memory 920, chipset,and processor 902. Examples may include, without limitation, an audiocontroller 929, a firmware hub (“flash BIOS”) 928, a wirelesstransceiver 926, a data storage 924, a legacy I/O controller 923containing user input and keyboard interfaces 925, a serial expansionport 927, such as Universal Serial Bus (“USB”), and a network controller934. Data storage 924 may comprise a hard disk drive, a floppy diskdrive, a CD-ROM device, a flash memory device, or other mass storagedevice.

In at least one embodiment, FIG. 9 illustrates a system, which includesinterconnected hardware devices or “chips”, whereas in otherembodiments, FIG. 9 may illustrate an exemplary System on a Chip(“SoC”). In at least one embodiment, devices may be interconnected withproprietary interconnects, standardized interconnects (e.g., PCIe) orsome combination thereof. In at least one embodiment, one or morecomponents of computer system 900 are interconnected using computeexpress link (CXL) interconnects.

Inference and/or training logic 715 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 715 are provided belowin conjunction with FIGS. 7A and/or 7B. In at least one embodiment,inference and/or training logic 715 may be used in system FIG. 9 forinferencing or predicting operations based, at least in part, on weightparameters calculated using neural network training operations, neuralnetwork functions and/or architectures, or neural network use casesdescribed herein.

Such components can be used to render images using ray tracing-basedimportance sampling, which can be accelerated through hardware.

FIG. 10 is a block diagram illustrating an electronic device 1000 forutilizing a processor 1010, according to at least one embodiment. In atleast one embodiment, electronic device 1000 may be, for example andwithout limitation, a notebook, a tower server, a rack server, a bladeserver, a laptop, a desktop, a tablet, a mobile device, a phone, anembedded computer, or any other suitable electronic device.

In at least one embodiment, system 1000 may include, without limitation,processor 1010 communicatively coupled to any suitable number or kind ofcomponents, peripherals, modules, or devices. In at least oneembodiment, processor 1010 coupled using a bus or interface, such as a1° C. bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus,a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”)bus, a Serial Advance Technology Attachment (“SATA”) bus, a UniversalSerial Bus (“USB”) (versions 1, 2, 3), or a Universal AsynchronousReceiver/Transmitter (“UART”) bus. In at least one embodiment, FIG. 10illustrates a system, which includes interconnected hardware devices or“chips”, whereas in other embodiments, FIG. 10 may illustrate anexemplary System on a Chip (“SoC”). In at least one embodiment, devicesillustrated in FIG. 10 may be interconnected with proprietaryinterconnects, standardized interconnects (e.g., PCIe) or somecombination thereof. In at least one embodiment, one or more componentsof FIG. 10 are interconnected using compute express link (CXL)interconnects.

In at least one embodiment, FIG. 10 may include a display 1024, a touchscreen 1025, a touch pad 1030, a Near Field Communications unit (“NFC”)1045, a sensor hub 1040, a thermal sensor 1046, an Express Chipset(“EC”) 1035, a Trusted Platform Module (“TPM”) 1038, BIOS/firmware/flashmemory (“BIOS, FW Flash”) 1022, a DSP 1060, a drive 1020 such as a SolidState Disk (“SSD”) or a Hard Disk Drive (“HDD”), a wireless local areanetwork unit (“WLAN”) 1050, a Bluetooth unit 1052, a Wireless Wide AreaNetwork unit (“WWAN”) 1056, a Global Positioning System (GPS) 1055, acamera (“USB 3.0 camera”) 1054 such as a USB 3.0 camera, and/or a LowPower Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1015 implementedin, for example, LPDDR3 standard. These components may each beimplemented in any suitable manner.

In at least one embodiment, other components may be communicativelycoupled to processor 1010 through components discussed above. In atleast one embodiment, an accelerometer 1041, Ambient Light Sensor(“ALS”) 1042, compass 1043, and a gyroscope 1044 may be communicativelycoupled to sensor hub 1040. In at least one embodiment, thermal sensor1039, a fan 1037, a keyboard 1046, and a touch pad 1030 may becommunicatively coupled to EC 1035. In at least one embodiment, speaker1063, headphones 1064, and microphone (“mic”) 1065 may becommunicatively coupled to an audio unit (“audio codec and class d amp”)1062, which may in turn be communicatively coupled to DSP 1060. In atleast one embodiment, audio unit 1064 may include, for example andwithout limitation, an audio coder/decoder (“codec”) and a class Damplifier. In at least one embodiment, SIM card (“SIM”) 1057 may becommunicatively coupled to WWAN unit 1056. In at least one embodiment,components such as WLAN unit 1050 and Bluetooth unit 1052, as well asWWAN unit 1056 may be implemented in a Next Generation Form Factor(“NGFF”).

Inference and/or training logic 715 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 715 are provided belowin conjunction with FIGS. 7 a and/or 7 b. In at least one embodiment,inference and/or training logic 715 may be used in system FIG. 10 forinferencing or predicting operations based, at least in part, on weightparameters calculated using neural network training operations, neuralnetwork functions and/or architectures, or neural network use casesdescribed herein.

Such components can be used to render images using ray tracing-basedimportance sampling, which can be accelerated through hardware.

FIG. 11 is a block diagram of a processing system, according to at leastone embodiment. In at least one embodiment, system 1100 includes one ormore processors 1102 and one or more graphics processors 1108, and maybe a single processor desktop system, a multiprocessor workstationsystem, or a server system having a large number of processors 1102 orprocessor cores 1107. In at least one embodiment, system 1100 is aprocessing platform incorporated within a system-on-a-chip (SoC)integrated circuit for use in mobile, handheld, or embedded devices.

In at least one embodiment, system 1100 can include, or be incorporatedwithin a server-based gaming platform, a game console, including a gameand media console, a mobile gaming console, a handheld game console, oran online game console. In at least one embodiment, system 1100 is amobile phone, smart phone, tablet computing device or mobile Internetdevice. In at least one embodiment, processing system 1100 can alsoinclude, couple with, or be integrated within a wearable device, such asa smart watch wearable device, smart eyewear device, augmented realitydevice, or virtual reality device. In at least one embodiment,processing system 1100 is a television or set top box device having oneor more processors 1102 and a graphical interface generated by one ormore graphics processors 1108.

In at least one embodiment, one or more processors 1102 each include oneor more processor cores 1107 to process instructions which, whenexecuted, perform operations for system and user software. In at leastone embodiment, each of one or more processor cores 1107 is configuredto process a specific instruction set 1109. In at least one embodiment,instruction set 1109 may facilitate Complex Instruction Set Computing(CISC), Reduced Instruction Set Computing (RISC), or computing via aVery Long Instruction Word (VLIW). In at least one embodiment, processorcores 1107 may each process a different instruction set 1109, which mayinclude instructions to facilitate emulation of other instruction sets.In at least one embodiment, processor core 1107 may also include otherprocessing devices, such a Digital Signal Processor (DSP).

In at least one embodiment, processor 1102 includes cache memory 1104.In at least one embodiment, processor 1102 can have a single internalcache or multiple levels of internal cache. In at least one embodiment,cache memory is shared among various components of processor 1102. In atleast one embodiment, processor 1102 also uses an external cache (e.g.,a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which maybe shared among processor cores 1107 using known cache coherencytechniques. In at least one embodiment, register file 1106 isadditionally included in processor 1102 which may include differenttypes of registers for storing different types of data (e.g., integerregisters, floating point registers, status registers, and aninstruction pointer register). In at least one embodiment, register file1106 may include general-purpose registers or other registers.

In at least one embodiment, one or more processor(s) 1102 are coupledwith one or more interface bus(es) 1110 to transmit communicationsignals such as address, data, or control signals between processor 1102and other components in system 1100. In at least one embodiment,interface bus 1110, in one embodiment, can be a processor bus, such as aversion of a Direct Media Interface (DMI) bus. In at least oneembodiment, interface 1110 is not limited to a DMI bus, and may includeone or more Peripheral Component Interconnect buses (e.g., PCI, PCIExpress), memory busses, or other types of interface busses. In at leastone embodiment processor(s) 1102 include an integrated memory controller1116 and a platform controller hub 1130. In at least one embodiment,memory controller 1116 facilitates communication between a memory deviceand other components of system 1100, while platform controller hub (PCH)1130 provides connections to I/O devices via a local I/O bus.

In at least one embodiment, memory device 1120 can be a dynamic randomaccess memory (DRAM) device, a static random access memory (SRAM)device, flash memory device, phase-change memory device, or some othermemory device having suitable performance to serve as process memory. Inat least one embodiment memory device 1120 can operate as system memoryfor system 1100, to store data 1122 and instructions 1121 for use whenone or more processors 1102 executes an application or process. In atleast one embodiment, memory controller 1116 also couples with anoptional external graphics processor 1112, which may communicate withone or more graphics processors 1108 in processors 1102 to performgraphics and media operations. In at least one embodiment, a displaydevice 1111 can connect to processor(s) 1102. In at least one embodimentdisplay device 1111 can include one or more of an internal displaydevice, as in a mobile electronic device or a laptop device or anexternal display device attached via a display interface (e.g.,DisplayPort, etc.). In at least one embodiment, display device 1111 caninclude a head mounted display (HMD) such as a stereoscopic displaydevice for use in virtual reality (VR) applications or augmented reality(AR) applications.

In at least one embodiment, platform controller hub 1130 enablesperipherals to connect to memory device 1120 and processor 1102 via ahigh-speed I/O bus. In at least one embodiment, I/O peripherals include,but are not limited to, an audio controller 1146, a network controller1134, a firmware interface 1128, a wireless transceiver 1126, touchsensors 1125, a data storage device 1124 (e.g., hard disk drive, flashmemory, etc.). In at least one embodiment, data storage device 1124 canconnect via a storage interface (e.g., SATA) or via a peripheral bus,such as a Peripheral Component Interconnect bus (e.g., PCI, PCIExpress). In at least one embodiment, touch sensors 1125 can includetouch screen sensors, pressure sensors, or fingerprint sensors. In atleast one embodiment, wireless transceiver 1126 can be a Wi-Fitransceiver, a Bluetooth transceiver, or a mobile network transceiversuch as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at leastone embodiment, firmware interface 1128 enables communication withsystem firmware, and can be, for example, a unified extensible firmwareinterface (UEFI). In at least one embodiment, network controller 1134can enable a network connection to a wired network. In at least oneembodiment, a high-performance network controller (not shown) coupleswith interface bus 1110. In at least one embodiment, audio controller1146 is a multi-channel high definition audio controller. In at leastone embodiment, system 1100 includes an optional legacy I/O controller1140 for coupling legacy (e.g., Personal System 2 (PS/2)) devices tosystem. In at least one embodiment, platform controller hub 1130 canalso connect to one or more Universal Serial Bus (USB) controllers 1142connect input devices, such as keyboard and mouse 1143 combinations, acamera 1144, or other USB input devices.

In at least one embodiment, an instance of memory controller 1116 andplatform controller hub 1130 may be integrated into a discreet externalgraphics processor, such as external graphics processor 1112. In atleast one embodiment, platform controller hub 1130 and/or memorycontroller 1116 may be external to one or more processor(s) 1102. Forexample, in at least one embodiment, system 1100 can include an externalmemory controller 1116 and platform controller hub 1130, which may beconfigured as a memory controller hub and peripheral controller hubwithin a system chipset that is in communication with processor(s) 1102.

Inference and/or training logic 715 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 715 are provided belowin conjunction with FIGS. 7A and/or 7B. In at least one embodimentportions or all of inference and/or training logic 715 may beincorporated into graphics processor 1500. For example, in at least oneembodiment, training and/or inferencing techniques described herein mayuse one or more of ALUs embodied in a graphics processor. Moreover, inat least one embodiment, inferencing and/or training operationsdescribed herein may be done using logic other than logic illustrated inFIG. 7A or 7B. In at least one embodiment, weight parameters may bestored in on-chip or off-chip memory and/or registers (shown or notshown) that configure ALUs of a graphics processor to perform one ormore machine learning algorithms, neural network architectures, usecases, or training techniques described herein.

Such components can be used to render images using ray tracing-basedimportance sampling, which can be accelerated through hardware.

FIG. 12 is a block diagram of a processor 1200 having one or moreprocessor cores 1202A-1202N, an integrated memory controller 1214, andan integrated graphics processor 1208, according to at least oneembodiment. In at least one embodiment, processor 1200 can includeadditional cores up to and including additional core 1202N representedby dashed lined boxes. In at least one embodiment, each of processorcores 1202A-1202N includes one or more internal cache units 1204A-1204N.In at least one embodiment, each processor core also has access to oneor more shared cached units 1206.

In at least one embodiment, internal cache units 1204A-1204N and sharedcache units 1206 represent a cache memory hierarchy within processor1200. In at least one embodiment, cache memory units 1204A-1204N mayinclude at least one level of instruction and data cache within eachprocessor core and one or more levels of shared mid-level cache, such asa Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache,where a highest level of cache before external memory is classified asan LLC. In at least one embodiment, cache coherency logic maintainscoherency between various cache units 1206 and 1204A-1204N.

In at least one embodiment, processor 1200 may also include a set of oneor more bus controller units 1216 and a system agent core 1210. In atleast one embodiment, one or more bus controller units 1216 manage a setof peripheral buses, such as one or more PCI or PCI express busses. Inat least one embodiment, system agent core 1210 provides managementfunctionality for various processor components. In at least oneembodiment, system agent core 1210 includes one or more integratedmemory controllers 1214 to manage access to various external memorydevices (not shown).

In at least one embodiment, one or more of processor cores 1202A-1202Ninclude support for simultaneous multi-threading. In at least oneembodiment, system agent core 1210 includes components for coordinatingand operating cores 1202A-1202N during multi-threaded processing. In atleast one embodiment, system agent core 1210 may additionally include apower control unit (PCU), which includes logic and components toregulate one or more power states of processor cores 1202A-1202N andgraphics processor 1208.

In at least one embodiment, processor 1200 additionally includesgraphics processor 1208 to execute graphics processing operations. In atleast one embodiment, graphics processor 1208 couples with shared cacheunits 1206, and system agent core 1210, including one or more integratedmemory controllers 1214. In at least one embodiment, system agent core1210 also includes a display controller 1211 to drive graphics processoroutput to one or more coupled displays. In at least one embodiment,display controller 1211 may also be a separate module coupled withgraphics processor 1208 via at least one interconnect, or may beintegrated within graphics processor 1208.

In at least one embodiment, a ring based interconnect unit 1212 is usedto couple internal components of processor 1200. In at least oneembodiment, an alternative interconnect unit may be used, such as apoint-to-point interconnect, a switched interconnect, or othertechniques. In at least one embodiment, graphics processor 1208 coupleswith ring interconnect 1212 via an I/O link 1213.

In at least one embodiment, I/O link 1213 represents at least one ofmultiple varieties of I/O interconnects, including an on package I/Ointerconnect which facilitates communication between various processorcomponents and a high-performance embedded memory module 1218, such asan eDRAM module. In at least one embodiment, each of processor cores1202A-1202N and graphics processor 1208 use embedded memory modules 1218as a shared Last Level Cache.

In at least one embodiment, processor cores 1202A-1202N are homogenouscores executing a common instruction set architecture. In at least oneembodiment, processor cores 1202A-1202N are heterogeneous in terms ofinstruction set architecture (ISA), where one or more of processor cores1202A-1202N execute a common instruction set, while one or more othercores of processor cores 1202A-1202N executes a subset of a commoninstruction set or a different instruction set. In at least oneembodiment, processor cores 1202A-1202N are heterogeneous in terms ofmicroarchitecture, where one or more cores having a relatively higherpower consumption couple with one or more power cores having a lowerpower consumption. In at least one embodiment, processor 1200 can beimplemented on one or more chips or as an SoC integrated circuit.

Inference and/or training logic 715 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 715 are provided belowin conjunction with FIGS. 7 a and/or 7 b. In at least one embodimentportions or all of inference and/or training logic 715 may beincorporated into processor 1200. For example, in at least oneembodiment, training and/or inferencing techniques described herein mayuse one or more of ALUs embodied in graphics processor 1512, graphicscore(s) 1202A-1202N, or other components in FIG. 12 . Moreover, in atleast one embodiment, inferencing and/or training operations describedherein may be done using logic other than logic illustrated in FIG. 7Aor 7B. In at least one embodiment, weight parameters may be stored inon-chip or off-chip memory and/or registers (shown or not shown) thatconfigure ALUs of graphics processor 1200 to perform one or more machinelearning algorithms, neural network architectures, use cases, ortraining techniques described herein.

Such components can be used to render images using ray tracing-basedimportance sampling, which can be accelerated through hardware.

Virtualized Computing Platform

FIG. 13 is an example data flow diagram for a process 1300 of generatingand deploying an image processing and inferencing pipeline, inaccordance with at least one embodiment. In at least one embodiment,process 1300 may be deployed for use with imaging devices, processingdevices, and/or other device types at one or more facilities 1302.Process 1300 may be executed within a training system 1304 and/or adeployment system 1306. In at least one embodiment, training system 1304may be used to perform training, deployment, and implementation ofmachine learning models (e.g., neural networks, object detectionalgorithms, computer vision algorithms, etc.) for use in deploymentsystem 1306. In at least one embodiment, deployment system 1306 may beconfigured to offload processing and compute resources among adistributed computing environment to reduce infrastructure requirementsat facility 1302. In at least one embodiment, one or more applicationsin a pipeline may use or call upon services (e.g., inference,visualization, compute, AI, etc.) of deployment system 1306 duringexecution of applications.

In at least one embodiment, some of applications used in advancedprocessing and inferencing pipelines may use machine learning models orother AI to perform one or more processing steps. In at least oneembodiment, machine learning models may be trained at facility 1302using data 1308 (such as imaging data) generated at facility 1302 (andstored on one or more picture archiving and communication system (PACS)servers at facility 1302), may be trained using imaging or sequencingdata 1308 from another facility(ies), or a combination thereof. In atleast one embodiment, training system 1304 may be used to provideapplications, services, and/or other resources for generating working,deployable machine learning models for deployment system 1306.

In at least one embodiment, model registry 1324 may be backed by objectstorage that may support versioning and object metadata. In at least oneembodiment, object storage may be accessible through, for example, acloud storage (e.g., cloud 1426 of FIG. 14 ) compatible applicationprogramming interface (API) from within a cloud platform. In at leastone embodiment, machine learning models within model registry 1324 mayuploaded, listed, modified, or deleted by developers or partners of asystem interacting with an API. In at least one embodiment, an API mayprovide access to methods that allow users with appropriate credentialsto associate models with applications, such that models may be executedas part of execution of containerized instantiations of applications.

In at least one embodiment, training pipeline 1404 (FIG. 14 ) mayinclude a scenario where facility 1302 is training their own machinelearning model, or has an existing machine learning model that needs tobe optimized or updated. In at least one embodiment, imaging data 1308generated by imaging device(s), sequencing devices, and/or other devicetypes may be received. In at least one embodiment, once imaging data1308 is received, AI-assisted annotation 1310 may be used to aid ingenerating annotations corresponding to imaging data 1308 to be used asground truth data for a machine learning model. In at least oneembodiment, AI-assisted annotation 1310 may include one or more machinelearning models (e.g., convolutional neural networks (CNNs)) that may betrained to generate annotations corresponding to certain types ofimaging data 1308 (e.g., from certain devices). In at least oneembodiment, AI-assisted annotations 1310 may then be used directly, ormay be adjusted or fine-tuned using an annotation tool to generateground truth data. In at least one embodiment, AI-assisted annotations1310, labeled clinic data 1312, or a combination thereof may be used asground truth data for training a machine learning model. In at least oneembodiment, a trained machine learning model may be referred to asoutput model 1316, and may be used by deployment system 1306, asdescribed herein.

In at least one embodiment, training pipeline 1404 (FIG. 14 ) mayinclude a scenario where facility 1302 needs a machine learning modelfor use in performing one or more processing tasks for one or moreapplications in deployment system 1306, but facility 1302 may notcurrently have such a machine learning model (or may not have a modelthat is optimized, efficient, or effective for such purposes). In atleast one embodiment, an existing machine learning model may be selectedfrom a model registry 1324. In at least one embodiment, model registry1324 may include machine learning models trained to perform a variety ofdifferent inference tasks on imaging data. In at least one embodiment,machine learning models in model registry 1324 may have been trained onimaging data from different facilities than facility 1302 (e.g.,facilities remotely located). In at least one embodiment, machinelearning models may have been trained on imaging data from one location,two locations, or any number of locations. In at least one embodiment,when being trained on imaging data from a specific location, trainingmay take place at that location, or at least in a manner that protectsconfidentiality of imaging data or restricts imaging data from beingtransferred off-premises. In at least one embodiment, once a model istrained—or partially trained—at one location, a machine learning modelmay be added to model registry 1324. In at least one embodiment, amachine learning model may then be retrained, or updated, at any numberof other facilities, and a retrained or updated model may be madeavailable in model registry 1324. In at least one embodiment, a machinelearning model may then be selected from model registry 1324—andreferred to as output model 1316—and may be used in deployment system1306 to perform one or more processing tasks for one or moreapplications of a deployment system.

In at least one embodiment, training pipeline 1404 (FIG. 14 ), ascenario may include facility 1302 requiring a machine learning modelfor use in performing one or more processing tasks for one or moreapplications in deployment system 1306, but facility 1302 may notcurrently have such a machine learning model (or may not have a modelthat is optimized, efficient, or effective for such purposes). In atleast one embodiment, a machine learning model selected from modelregistry 1324 may not be fine-tuned or optimized for imaging data 1308generated at facility 1302 because of differences in populations,robustness of training data used to train a machine learning model,diversity in anomalies of training data, and/or other issues withtraining data. In at least one embodiment, AI-assisted annotation 1310may be used to aid in generating annotations corresponding to imagingdata 1308 to be used as ground truth data for retraining or updating amachine learning model. In at least one embodiment, labeled data 1312may be used as ground truth data for training a machine learning model.In at least one embodiment, retraining or updating a machine learningmodel may be referred to as model training 1314. In at least oneembodiment, model training 1314—e.g., AI-assisted annotations 1310,labeled clinic data 1312, or a combination thereof—may be used as groundtruth data for retraining or updating a machine learning model. In atleast one embodiment, a trained machine learning model may be referredto as output model 1316, and may be used by deployment system 1306, asdescribed herein.

In at least one embodiment, deployment system 1306 may include software1318, services 1320, hardware 1322, and/or other components, features,and functionality. In at least one embodiment, deployment system 1306may include a software “stack,” such that software 1318 may be built ontop of services 1320 and may use services 1320 to perform some or all ofprocessing tasks, and services 1320 and software 1318 may be built ontop of hardware 1322 and use hardware 1322 to execute processing,storage, and/or other compute tasks of deployment system 1306. In atleast one embodiment, software 1318 may include any number of differentcontainers, where each container may execute an instantiation of anapplication. In at least one embodiment, each application may performone or more processing tasks in an advanced processing and inferencingpipeline (e.g., inferencing, object detection, feature detection,segmentation, image enhancement, calibration, etc.). In at least oneembodiment, an advanced processing and inferencing pipeline may bedefined based on selections of different containers that are desired orrequired for processing imaging data 1308, in addition to containersthat receive and configure imaging data for use by each container and/orfor use by facility 1302 after processing through a pipeline (e.g., toconvert outputs back to a usable data type). In at least one embodiment,a combination of containers within software 1318 (e.g., that make up apipeline) may be referred to as a virtual instrument (as described inmore detail herein), and a virtual instrument may leverage services 1320and hardware 1322 to execute some or all processing tasks ofapplications instantiated in containers.

In at least one embodiment, a data processing pipeline may receive inputdata (e.g., imaging data 1308) in a specific format in response to aninference request (e.g., a request from a user of deployment system1306). In at least one embodiment, input data may be representative ofone or more images, video, and/or other data representations generatedby one or more imaging devices. In at least one embodiment, data mayundergo pre-processing as part of data processing pipeline to preparedata for processing by one or more applications. In at least oneembodiment, post-processing may be performed on an output of one or moreinferencing tasks or other processing tasks of a pipeline to prepare anoutput data for a next application and/or to prepare output data fortransmission and/or use by a user (e.g., as a response to an inferencerequest). In at least one embodiment, inferencing tasks may be performedby one or more machine learning models, such as trained or deployedneural networks, which may include output models 1316 of training system1304.

In at least one embodiment, tasks of data processing pipeline may beencapsulated in a container(s) that each represents a discrete, fullyfunctional instantiation of an application and virtualized computingenvironment that is able to reference machine learning models. In atleast one embodiment, containers or applications may be published into aprivate (e.g., limited access) area of a container registry (describedin more detail herein), and trained or deployed models may be stored inmodel registry 1324 and associated with one or more applications. In atleast one embodiment, images of applications (e.g., container images)may be available in a container registry, and once selected by a userfrom a container registry for deployment in a pipeline, an image may beused to generate a container for an instantiation of an application foruse by a user's system.

In at least one embodiment, developers (e.g., software developers,clinicians, doctors, etc.) may develop, publish, and store applications(e.g., as containers) for performing image processing and/or inferencingon supplied data. In at least one embodiment, development, publishing,and/or storing may be performed using a software development kit (SDK)associated with a system (e.g., to ensure that an application and/orcontainer developed is compliant with or compatible with a system). Inat least one embodiment, an application that is developed may be testedlocally (e.g., at a first facility, on data from a first facility) withan SDK which may support at least some of services 1320 as a system(e.g., system 1400 of FIG. 14 ). In at least one embodiment, becauseDICOM objects may contain anywhere from one to hundreds of images orother data types, and due to a variation in data, a developer may beresponsible for managing (e.g., setting constructs for, buildingpre-processing into an application, etc.) extraction and preparation ofincoming data. In at least one embodiment, once validated by system 1400(e.g., for accuracy), an application may be available in a containerregistry for selection and/or implementation by a user to perform one ormore processing tasks with respect to data at a facility (e.g., a secondfacility) of a user.

In at least one embodiment, developers may then share applications orcontainers through a network for access and use by users of a system(e.g., system 1400 of FIG. 14 ). In at least one embodiment, completedand validated applications or containers may be stored in a containerregistry and associated machine learning models may be stored in modelregistry 1324. In at least one embodiment, a requesting entity—whoprovides an inference or image processing request—may browse a containerregistry and/or model registry 1324 for an application, container,dataset, machine learning model, etc., select a desired combination ofelements for inclusion in data processing pipeline, and submit animaging processing request. In at least one embodiment, a request mayinclude input data (and associated patient data, in some examples) thatis necessary to perform a request, and/or may include a selection ofapplication(s) and/or machine learning models to be executed inprocessing a request. In at least one embodiment, a request may then bepassed to one or more components of deployment system 1306 (e.g., acloud) to perform processing of data processing pipeline. In at leastone embodiment, processing by deployment system 1306 may includereferencing selected elements (e.g., applications, containers, models,etc.) from a container registry and/or model registry 1324. In at leastone embodiment, once results are generated by a pipeline, results may bereturned to a user for reference (e.g., for viewing in a viewingapplication suite executing on a local, on-premises workstation orterminal).

In at least one embodiment, to aid in processing or execution ofapplications or containers in pipelines, services 1320 may be leveraged.In at least one embodiment, services 1320 may include compute services,artificial intelligence (AI) services, visualization services, and/orother service types. In at least one embodiment, services 1320 mayprovide functionality that is common to one or more applications insoftware 1318, so functionality may be abstracted to a service that maybe called upon or leveraged by applications. In at least one embodiment,functionality provided by services 1320 may run dynamically and moreefficiently, while also scaling well by allowing applications to processdata in parallel (e.g., using a parallel computing platform 1430 (FIG.14 )). In at least one embodiment, rather than each application thatshares a same functionality offered by a service 1320 being required tohave a respective instance of service 1320, service 1320 may be sharedbetween and among various applications. In at least one embodiment,services may include an inference server or engine that may be used forexecuting detection or segmentation tasks, as non-limiting examples. Inat least one embodiment, a model training service may be included thatmay provide machine learning model training and/or retrainingcapabilities. In at least one embodiment, a data augmentation servicemay further be included that may provide GPU accelerated data (e.g.,DICOM, RIS, CIS, REST compliant, RPC, raw, etc.) extraction, resizing,scaling, and/or other augmentation. In at least one embodiment, avisualization service may be used that may add image renderingeffects—such as ray-tracing, rasterization, denoising, sharpening,etc.—to add realism to two-dimensional (2D) and/or three-dimensional(3D) models. In at least one embodiment, virtual instrument services maybe included that provide for beam-forming, segmentation, inferencing,imaging, and/or support for other applications within pipelines ofvirtual instruments.

In at least one embodiment, where a service 1320 includes an AI service(e.g., an inference service), one or more machine learning models may beexecuted by calling upon (e.g., as an API call) an inference service(e.g., an inference server) to execute machine learning model(s), orprocessing thereof, as part of application execution. In at least oneembodiment, where another application includes one or more machinelearning models for segmentation tasks, an application may call upon aninference service to execute machine learning models for performing oneor more of processing operations associated with segmentation tasks. Inat least one embodiment, software 1318 implementing advanced processingand inferencing pipeline that includes segmentation application andanomaly detection application may be streamlined because eachapplication may call upon a same inference service to perform one ormore inferencing tasks.

In at least one embodiment, hardware 1322 may include GPUs, CPUs,graphics cards, an AI/deep learning system (e.g., an AI supercomputer,such as NVIDIA's DGX), a cloud platform, or a combination thereof. In atleast one embodiment, different types of hardware 1322 may be used toprovide efficient, purpose-built support for software 1318 and services1320 in deployment system 1306. In at least one embodiment, use of GPUprocessing may be implemented for processing locally (e.g., at facility1302), within an AI/deep learning system, in a cloud system, and/or inother processing components of deployment system 1306 to improveefficiency, accuracy, and efficacy of image processing and generation.In at least one embodiment, software 1318 and/or services 1320 may beoptimized for GPU processing with respect to deep learning, machinelearning, and/or high-performance computing, as non-limiting examples.In at least one embodiment, at least some of computing environment ofdeployment system 1306 and/or training system 1304 may be executed in adatacenter one or more supercomputers or high performance computingsystems, with GPU optimized software (e.g., hardware and softwarecombination of NVIDIA's DGX System). In at least one embodiment,hardware 1322 may include any number of GPUs that may be called upon toperform processing of data in parallel, as described herein. In at leastone embodiment, cloud platform may further include GPU processing forGPU-optimized execution of deep learning tasks, machine learning tasks,or other computing tasks. In at least one embodiment, cloud platform(e.g., NVIDIA's NGC) may be executed using an AI/deep learningsupercomputer(s) and/or GPU-optimized software (e.g., as provided onNVIDIA's DGX Systems) as a hardware abstraction and scaling platform. Inat least one embodiment, cloud platform may integrate an applicationcontainer clustering system or orchestration system (e.g., KUBERNETES)on multiple GPUs to enable seamless scaling and load balancing.

FIG. 14 is a system diagram for an example system 1400 for generatingand deploying an imaging deployment pipeline, in accordance with atleast one embodiment. In at least one embodiment, system 1400 may beused to implement process 1300 of FIG. 13 and/or other processesincluding advanced processing and inferencing pipelines. In at least oneembodiment, system 1400 may include training system 1304 and deploymentsystem 1306. In at least one embodiment, training system 1304 anddeployment system 1306 may be implemented using software 1318, services1320, and/or hardware 1322, as described herein.

In at least one embodiment, system 1400 (e.g., training system 1304and/or deployment system 1306) may implemented in a cloud computingenvironment (e.g., using cloud 1426). In at least one embodiment, system1400 may be implemented locally with respect to a healthcare servicesfacility, or as a combination of both cloud and local computingresources. In at least one embodiment, access to APIs in cloud 1426 maybe restricted to authorized users through enacted security measures orprotocols. In at least one embodiment, a security protocol may includeweb tokens that may be signed by an authentication (e.g., AuthN, AuthZ,Gluecon, etc.) service and may carry appropriate authorization. In atleast one embodiment, APIs of virtual instruments (described herein), orother instantiations of system 1400, may be restricted to a set ofpublic IPs that have been vetted or authorized for interaction.

In at least one embodiment, various components of system 1400 maycommunicate between and among one another using any of a variety ofdifferent network types, including but not limited to local areanetworks (LANs) and/or wide area networks (WANs) via wired and/orwireless communication protocols. In at least one embodiment,communication between facilities and components of system 1400 (e.g.,for transmitting inference requests, for receiving results of inferencerequests, etc.) may be communicated over data bus(ses), wireless dataprotocols (Wi-Fi), wired data protocols (e.g., Ethernet), etc.

In at least one embodiment, training system 1304 may execute trainingpipelines 1404, similar to those described herein with respect to FIG.13 . In at least one embodiment, where one or more machine learningmodels are to be used in deployment pipelines 1410 by deployment system1306, training pipelines 1404 may be used to train or retrain one ormore (e.g. pre-trained) models, and/or implement one or more ofpre-trained models 1406 (e.g., without a need for retraining orupdating). In at least one embodiment, as a result of training pipelines1404, output model(s) 1316 may be generated. In at least one embodiment,training pipelines 1404 may include any number of processing steps, suchas but not limited to imaging data (or other input data) conversion oradaption In at least one embodiment, for different machine learningmodels used by deployment system 1306, different training pipelines 1404may be used. In at least one embodiment, training pipeline 1404 similarto a first example described with respect to FIG. 13 may be used for afirst machine learning model, training pipeline 1404 similar to a secondexample described with respect to FIG. 13 may be used for a secondmachine learning model, and training pipeline 1404 similar to a thirdexample described with respect to FIG. 13 may be used for a thirdmachine learning model. In at least one embodiment, any combination oftasks within training system 1304 may be used depending on what isrequired for each respective machine learning model. In at least oneembodiment, one or more of machine learning models may already betrained and ready for deployment so machine learning models may notundergo any processing by training system 1304, and may be implementedby deployment system 1306.

In at least one embodiment, output model(s) 1316 and/or pre-trainedmodel(s) 1406 may include any types of machine learning models dependingon implementation or embodiment. In at least one embodiment, and withoutlimitation, machine learning models used by system 1400 may includemachine learning model(s) using linear regression, logistic regression,decision trees, support vector machines (SVM), Naïve Bayes, k-nearestneighbor (Knn), K means clustering, random forest, dimensionalityreduction algorithms, gradient boosting algorithms, neural networks(e.g., auto-encoders, convolutional, recurrent, perceptrons, Long/ShortTerm Memory (LSTM), Hopfield, Boltzmann, deep belief, deconvolutional,generative adversarial, liquid state machine, etc.), and/or other typesof machine learning models.

In at least one embodiment, training pipelines 1404 may includeAI-assisted annotation, as described in more detail herein with respectto at least FIG. 15B. In at least one embodiment, labeled data 1312(e.g., traditional annotation) may be generated by any number oftechniques. In at least one embodiment, labels or other annotations maybe generated within a drawing program (e.g., an annotation program), acomputer aided design (CAD) program, a labeling program, another type ofprogram suitable for generating annotations or labels for ground truth,and/or may be hand drawn, in some examples. In at least one embodiment,ground truth data may be synthetically produced (e.g., generated fromcomputer models or renderings), real produced (e.g., designed andproduced from real-world data), machine-automated (e.g., using featureanalysis and learning to extract features from data and then generatelabels), human annotated (e.g., labeler, or annotation expert, defineslocation of labels), and/or a combination thereof. In at least oneembodiment, for each instance of imaging data 1308 (or other data typeused by machine learning models), there may be corresponding groundtruth data generated by training system 1304. In at least oneembodiment, AI-assisted annotation may be performed as part ofdeployment pipelines 1410; either in addition to, or in lieu ofAI-assisted annotation included in training pipelines 1404. In at leastone embodiment, system 1400 may include a multi-layer platform that mayinclude a software layer (e.g., software 1318) of diagnosticapplications (or other application types) that may perform one or moremedical imaging and diagnostic functions. In at least one embodiment,system 1400 may be communicatively coupled to (e.g., via encryptedlinks) PACS server networks of one or more facilities. In at least oneembodiment, system 1400 may be configured to access and referenced datafrom PACS servers to perform operations, such as training machinelearning models, deploying machine learning models, image processing,inferencing, and/or other operations.

In at least one embodiment, a software layer may be implemented as asecure, encrypted, and/or authenticated API through which applicationsor containers may be invoked (e.g., called) from an externalenvironment(s) (e.g., facility 1302). In at least one embodiment,applications may then call or execute one or more services 1320 forperforming compute, AI, or visualization tasks associated withrespective applications, and software 1318 and/or services 1320 mayleverage hardware 1322 to perform processing tasks in an effective andefficient manner.

In at least one embodiment, deployment system 1306 may executedeployment pipelines 1410. In at least one embodiment, deploymentpipelines 1410 may include any number of applications that may besequentially, non-sequentially, or otherwise applied to imaging data(and/or other data types) generated by imaging devices, sequencingdevices, genomics devices, etc.—including AI-assisted annotation, asdescribed above. In at least one embodiment, as described herein, adeployment pipeline 1410 for an individual device may be referred to asa virtual instrument for a device (e.g., a virtual ultrasoundinstrument, a virtual CT scan instrument, a virtual sequencinginstrument, etc.). In at least one embodiment, for a single device,there may be more than one deployment pipeline 1410 depending oninformation desired from data generated by a device. In at least oneembodiment, where detections of anomalies are desired from an MRImachine, there may be a first deployment pipeline 1410, and where imageenhancement is desired from output of an MRI machine, there may be asecond deployment pipeline 1410.

In at least one embodiment, an image generation application may includea processing task that includes use of a machine learning model. In atleast one embodiment, a user may desire to use their own machinelearning model, or to select a machine learning model from modelregistry 1324. In at least one embodiment, a user may implement theirown machine learning model or select a machine learning model forinclusion in an application for performing a processing task. In atleast one embodiment, applications may be selectable and customizable,and by defining constructs of applications, deployment andimplementation of applications for a particular user are presented as amore seamless user experience. In at least one embodiment, by leveragingother features of system 1400—such as services 1320 and hardware1322—deployment pipelines 1410 may be even more user friendly, providefor easier integration, and produce more accurate, efficient, and timelyresults.

In at least one embodiment, deployment system 1306 may include a userinterface 1414 (e.g., a graphical user interface, a web interface, etc.)that may be used to select applications for inclusion in deploymentpipeline(s) 1410, arrange applications, modify or change applications orparameters or constructs thereof, use and interact with deploymentpipeline(s) 1410 during set-up and/or deployment, and/or to otherwiseinteract with deployment system 1306. In at least one embodiment,although not illustrated with respect to training system 1304, userinterface 1414 (or a different user interface) may be used for selectingmodels for use in deployment system 1306, for selecting models fortraining, or retraining, in training system 1304, and/or for otherwiseinteracting with training system 1304.

In at least one embodiment, pipeline manager 1412 may be used, inaddition to an application orchestration system 1428, to manageinteraction between applications or containers of deployment pipeline(s)1410 and services 1320 and/or hardware 1322. In at least one embodiment,pipeline manager 1412 may be configured to facilitate interactions fromapplication to application, from application to service 1320, and/orfrom application or service to hardware 1322. In at least oneembodiment, although illustrated as included in software 1318, this isnot intended to be limiting, and in some examples (e.g., as illustratedin FIG. 12 cc) pipeline manager 1412 may be included in services 1320.In at least one embodiment, application orchestration system 1428 (e.g.,Kubernetes, DOCKER, etc.) may include a container orchestration systemthat may group applications into containers as logical units forcoordination, management, scaling, and deployment. In at least oneembodiment, by associating applications from deployment pipeline(s) 1410(e.g., a reconstruction application, a segmentation application, etc.)with individual containers, each application may execute in aself-contained environment (e.g., at a kernel level) to increase speedand efficiency.

In at least one embodiment, each application and/or container (or imagethereof) may be individually developed, modified, and deployed (e.g., afirst user or developer may develop, modify, and deploy a firstapplication and a second user or developer may develop, modify, anddeploy a second application separate from a first user or developer),which may allow for focus on, and attention to, a task of a singleapplication and/or container(s) without being hindered by tasks ofanother application(s) or container(s). In at least one embodiment,communication, and cooperation between different containers orapplications may be aided by pipeline manager 1412 and applicationorchestration system 1428. In at least one embodiment, so long as anexpected input and/or output of each container or application is knownby a system (e.g., based on constructs of applications or containers),application orchestration system 1428 and/or pipeline manager 1412 mayfacilitate communication among and between, and sharing of resourcesamong and between, each of applications or containers. In at least oneembodiment, because one or more of applications or containers indeployment pipeline(s) 1410 may share same services and resources,application orchestration system 1428 may orchestrate, load balance, anddetermine sharing of services or resources between and among variousapplications or containers. In at least one embodiment, a scheduler maybe used to track resource requirements of applications or containers,current usage or planned usage of these resources, and resourceavailability. In at least one embodiment, a scheduler may thus allocateresources to different applications and distribute resources between andamong applications in view of requirements and availability of a system.In some examples, a scheduler (and/or other component of applicationorchestration system 1428) may determine resource availability anddistribution based on constraints imposed on a system (e.g., userconstraints), such as quality of service (QoS), urgency of need for dataoutputs (e.g., to determine whether to execute real-time processing ordelayed processing), etc.

In at least one embodiment, services 1320 leveraged by and shared byapplications or containers in deployment system 1306 may include computeservices 1416, AI services 1418, visualization services 1420, and/orother service types. In at least one embodiment, applications may call(e.g., execute) one or more of services 1320 to perform processingoperations for an application. In at least one embodiment, computeservices 1416 may be leveraged by applications to performsuper-computing or other high-performance computing (HPC) tasks. In atleast one embodiment, compute service(s) 1416 may be leveraged toperform parallel processing (e.g., using a parallel computing platform1430) for processing data through one or more of applications and/or oneor more tasks of a single application, substantially simultaneously. Inat least one embodiment, parallel computing platform 1430 (e.g.,NVIDIA's CUDA) may enable general purpose computing on GPUs (GPGPU)(e.g., GPUs 1422). In at least one embodiment, a software layer ofparallel computing platform 1430 may provide access to virtualinstruction sets and parallel computational elements of GPUs, forexecution of compute kernels. In at least one embodiment, parallelcomputing platform 1430 may include memory and, in some embodiments, amemory may be shared between and among multiple containers, and/orbetween and among different processing tasks within a single container.In at least one embodiment, inter-process communication (IPC) calls maybe generated for multiple containers and/or for multiple processeswithin a container to use same data from a shared segment of memory ofparallel computing platform 1430 (e.g., where multiple different stagesof an application or multiple applications are processing sameinformation). In at least one embodiment, rather than making a copy ofdata and moving data to different locations in memory (e.g., aread/write operation), same data in same location of a memory may beused for any number of processing tasks (e.g., at a same time, atdifferent times, etc.). In at least one embodiment, as data is used togenerate new data as a result of processing, this information of a newlocation of data may be stored and shared between various applications.In at least one embodiment, location of data and a location of updatedor modified data may be part of a definition of how a payload isunderstood within containers.

In at least one embodiment, AI services 1418 may be leveraged to performinferencing services for executing machine learning model(s) associatedwith applications (e.g., tasked with performing one or more processingtasks of an application). In at least one embodiment, AI services 1418may leverage AI system 1424 to execute machine learning model(s) (e.g.,neural networks, such as CNNs) for segmentation, reconstruction, objectdetection, feature detection, classification, and/or other inferencingtasks. In at least one embodiment, applications of deploymentpipeline(s) 1410 may use one or more of output models 1316 from trainingsystem 1304 and/or other models of applications to perform inference onimaging data. In at least one embodiment, two or more examples ofinferencing using application orchestration system 1428 (e.g., ascheduler) may be available. In at least one embodiment, a firstcategory may include a high priority/low latency path that may achievehigher service level agreements, such as for performing inference onurgent requests during an emergency, or for a radiologist duringdiagnosis. In at least one embodiment, a second category may include astandard priority path that may be used for requests that may benon-urgent or where analysis may be performed at a later time. In atleast one embodiment, application orchestration system 1428 maydistribute resources (e.g., services 1320 and/or hardware 1322) based onpriority paths for different inferencing tasks of AI services 1418.

In at least one embodiment, shared storage may be mounted to AI services1418 within system 1400. In at least one embodiment, shared storage mayoperate as a cache (or other storage device type) and may be used toprocess inference requests from applications. In at least oneembodiment, when an inference request is submitted, a request may bereceived by a set of API instances of deployment system 1306, and one ormore instances may be selected (e.g., for best fit, for load balancing,etc.) to process a request. In at least one embodiment, to process arequest, a request may be entered into a database, a machine learningmodel may be located from model registry 1324 if not already in a cache,a validation step may ensure appropriate machine learning model isloaded into a cache (e.g., shared storage), and/or a copy of a model maybe saved to a cache. In at least one embodiment, a scheduler (e.g., ofpipeline manager 1412) may be used to launch an application that isreferenced in a request if an application is not already running or ifthere are not enough instances of an application. In at least oneembodiment, if an inference server is not already launched to execute amodel, an inference server may be launched. Any number of inferenceservers may be launched per model. In at least one embodiment, in a pullmodel, in which inference servers are clustered, models may be cachedwhenever load balancing is advantageous. In at least one embodiment,inference servers may be statically loaded in corresponding, distributedservers.

In at least one embodiment, inferencing may be performed using aninference server that runs in a container. In at least one embodiment,an instance of an inference server may be associated with a model (andoptionally a plurality of versions of a model). In at least oneembodiment, if an instance of an inference server does not exist when arequest to perform inference on a model is received, a new instance maybe loaded. In at least one embodiment, when starting an inferenceserver, a model may be passed to an inference server such that a samecontainer may be used to serve different models so long as inferenceserver is running as a different instance.

In at least one embodiment, during application execution, an inferencerequest for a given application may be received, and a container (e.g.,hosting an instance of an inference server) may be loaded (if notalready), and a start procedure may be called. In at least oneembodiment, pre-processing logic in a container may load, decode, and/orperform any additional pre-processing on incoming data (e.g., using aCPU(s) and/or GPU(s)). In at least one embodiment, once data is preparedfor inference, a container may perform inference as necessary on data.In at least one embodiment, this may include a single inference call onone image (e.g., a hand X-ray), or may require inference on hundreds ofimages (e.g., a chest CT). In at least one embodiment, an applicationmay summarize results before completing, which may include, withoutlimitation, a single confidence score, pixel level-segmentation,voxel-level segmentation, generating a visualization, or generating textto summarize findings. In at least one embodiment, different models orapplications may be assigned different priorities. For example, somemodels may have a real-time (TAT<1 min) priority while others may havelower priority (e.g., TAT<10 min). In at least one embodiment, modelexecution times may be measured from requesting institution or entityand may include partner network traversal time, as well as execution onan inference service.

In at least one embodiment, transfer of requests between services 1320and inference applications may be hidden behind a software developmentkit (SDK), and robust transport may be provide through a queue. In atleast one embodiment, a request will be placed in a queue via an API foran individual application/tenant ID combination and an SDK will pull arequest from a queue and give a request to an application. In at leastone embodiment, a name of a queue may be provided in an environment fromwhere an SDK will pick it up. In at least one embodiment, asynchronouscommunication through a queue may be useful as it may allow any instanceof an application to pick up work as it becomes available. Results maybe transferred back through a queue, to ensure no data is lost. In atleast one embodiment, queues may also provide an ability to segmentwork, as highest priority work may go to a queue with most instances ofan application connected to it, while lowest priority work may go to aqueue with a single instance connected to it that processes tasks in anorder received. In at least one embodiment, an application may run on aGPU-accelerated instance generated in cloud 1426, and an inferenceservice may perform inferencing on a GPU.

In at least one embodiment, visualization services 1420 may be leveragedto generate visualizations for viewing outputs of applications and/ordeployment pipeline(s) 1410. In at least one embodiment, GPUs 1422 maybe leveraged by visualization services 1420 to generate visualizations.In at least one embodiment, rendering effects, such as ray-tracing, maybe implemented by visualization services 1420 to generate higher qualityvisualizations. In at least one embodiment, visualizations may include,without limitation, 2D image renderings, 3D volume renderings, 3D volumereconstruction, 2D tomographic slices, virtual reality displays,augmented reality displays, etc. In at least one embodiment, virtualizedenvironments may be used to generate a virtual interactive display orenvironment (e.g., a virtual environment) for interaction by users of asystem (e.g., doctors, nurses, radiologists, etc.). In at least oneembodiment, visualization services 1420 may include an internalvisualizer, cinematics, and/or other rendering or image processingcapabilities or functionality (e.g., ray tracing, rasterization,internal optics, etc.).

In at least one embodiment, hardware 1322 may include GPUs 1422, AIsystem 1424, cloud 1426, and/or any other hardware used for executingtraining system 1304 and/or deployment system 1306. In at least oneembodiment, GPUs 1422 (e.g., NVIDIA's TESLA and/or QUADRO GPUs) mayinclude any number of GPUs that may be used for executing processingtasks of compute services 1416, AI services 1418, visualization services1420, other services, and/or any of features or functionality ofsoftware 1318. For example, with respect to AI services 1418, GPUs 1422may be used to perform pre-processing on imaging data (or other datatypes used by machine learning models), post-processing on outputs ofmachine learning models, and/or to perform inferencing (e.g., to executemachine learning models). In at least one embodiment, cloud 1426, AIsystem 1424, and/or other components of system 1400 may use GPUs 1422.In at least one embodiment, cloud 1426 may include a GPU-optimizedplatform for deep learning tasks. In at least one embodiment, AI system1424 may use GPUs, and cloud 1426—or at least a portion tasked with deeplearning or inferencing—may be executed using one or more AI systems1424. As such, although hardware 1322 is illustrated as discretecomponents, this is not intended to be limiting, and any components ofhardware 1322 may be combined with, or leveraged by, any othercomponents of hardware 1322.

In at least one embodiment, AI system 1424 may include a purpose-builtcomputing system (e.g., a super-computer or an HPC) configured forinferencing, deep learning, machine learning, and/or other artificialintelligence tasks. In at least one embodiment, AI system 1424 (e.g.,NVIDIA's DGX) may include GPU-optimized software (e.g., a softwarestack) that may be executed using a plurality of GPUs 1422, in additionto CPUs, RAM, storage, and/or other components, features, orfunctionality. In at least one embodiment, one or more AI systems 1424may be implemented in cloud 1426 (e.g., in a data center) for performingsome or all of AI-based processing tasks of system 1400.

In at least one embodiment, cloud 1426 may include a GPU-acceleratedinfrastructure (e.g., NVIDIA's NGC) that may provide a GPU-optimizedplatform for executing processing tasks of system 1400. In at least oneembodiment, cloud 1426 may include an AI system(s) 1424 for performingone or more of AI-based tasks of system 1400 (e.g., as a hardwareabstraction and scaling platform). In at least one embodiment, cloud1426 may integrate with application orchestration system 1428 leveragingmultiple GPUs to enable seamless scaling and load balancing between andamong applications and services 1320. In at least one embodiment, cloud1426 may tasked with executing at least some of services 1320 of system1400, including compute services 1416, AI services 1418, and/orvisualization services 1420, as described herein. In at least oneembodiment, cloud 1426 may perform small and large batch inference(e.g., executing NVIDIA's TENSOR RT), provide an accelerated parallelcomputing API and platform 1430 (e.g., NVIDIA's CUDA), executeapplication orchestration system 1428 (e.g., KUBERNETES), provide agraphics rendering API and platform (e.g., for ray-tracing, 2D graphics,3D graphics, and/or other rendering techniques to produce higher qualitycinematics), and/or may provide other functionality for system 1400.

FIG. 15A illustrates a data flow diagram for a process 1500 to train,retrain, or update a machine learning model, in accordance with at leastone embodiment. In at least one embodiment, process 1500 may be executedusing, as a non-limiting example, system 1400 of FIG. 14 . In at leastone embodiment, process 1500 may leverage services 1320 and/or hardware1322 of system 1400, as described herein. In at least one embodiment,refined models 1512 generated by process 1500 may be executed bydeployment system 1306 for one or more containerized applications indeployment pipelines 1410.

In at least one embodiment, model training 1314 may include retrainingor updating an initial model 1504 (e.g., a pre-trained model) using newtraining data (e.g., new input data, such as customer dataset 1506,and/or new ground truth data associated with input data). In at leastone embodiment, to retrain, or update, initial model 1504, output orloss layer(s) of initial model 1504 may be reset, or deleted, and/orreplaced with an updated or new output or loss layer(s). In at least oneembodiment, initial model 1504 may have previously fine-tuned parameters(e.g., weights and/or biases) that remain from prior training, sotraining or retraining 1314 may not take as long or require as muchprocessing as training a model from scratch. In at least one embodiment,during model training 1314, by having reset or replaced output or losslayer(s) of initial model 1504, parameters may be updated and re-tunedfor a new data set based on loss calculations associated with accuracyof output or loss layer(s) at generating predictions on new, customerdataset 1506 (e.g., image data 1308 of FIG. 13 ).

In at least one embodiment, pre-trained models 1406 may be stored in adata store, or registry (e.g., model registry 1324 of FIG. 13 ). In atleast one embodiment, pre-trained models 1406 may have been trained, atleast in part, at one or more facilities other than a facility executingprocess 1500. In at least one embodiment, to protect privacy and rightsof patients, subjects, or clients of different facilities, pre-trainedmodels 1406 may have been trained, on-premise, using customer or patientdata generated on-premise. In at least one embodiment, pre-trainedmodels 1406 may be trained using cloud 1426 and/or other hardware 1322,but confidential, privacy protected patient data may not be transferredto, used by, or accessible to any components of cloud 1426 (or other offpremise hardware). In at least one embodiment, where a pre-trained model1406 is trained at using patient data from more than one facility,pre-trained model 1406 may have been individually trained for eachfacility prior to being trained on patient or customer data from anotherfacility. In at least one embodiment, such as where a customer orpatient data has been released of privacy concerns (e.g., by waiver, forexperimental use, etc.), or where a customer or patient data is includedin a public data set, a customer or patient data from any number offacilities may be used to train pre-trained model 1406 on-premise and/oroff premise, such as in a datacenter or other cloud computinginfrastructure.

In at least one embodiment, when selecting applications for use indeployment pipelines 1410, a user may also select machine learningmodels to be used for specific applications. In at least one embodiment,a user may not have a model for use, so a user may select a pre-trainedmodel 1406 to use with an application. In at least one embodiment,pre-trained model 1406 may not be optimized for generating accurateresults on customer dataset 1506 of a facility of a user (e.g., based onpatient diversity, demographics, types of medical imaging devices used,etc.). In at least one embodiment, prior to deploying pre-trained model1406 into deployment pipeline 1410 for use with an application(s),pre-trained model 1406 may be updated, retrained, and/or fine-tuned foruse at a respective facility.

In at least one embodiment, a user may select pre-trained model 1406that is to be updated, retrained, and/or fine-tuned, and pre-trainedmodel 1406 may be referred to as initial model 1504 for training system1304 within process 1500. In at least one embodiment, customer dataset1506 (e.g., imaging data, genomics data, sequencing data, or other datatypes generated by devices at a facility) may be used to perform modeltraining 1314 (which may include, without limitation, transfer learning)on initial model 1504 to generate refined model 1512. In at least oneembodiment, ground truth data corresponding to customer dataset 1506 maybe generated by training system 1304. In at least one embodiment, groundtruth data may be generated, at least in part, by clinicians,scientists, doctors, practitioners, at a facility (e.g., as labeledclinic data 1312 of FIG. 13 ).

In at least one embodiment, AI-assisted annotation 1310 may be used insome examples to generate ground truth data. In at least one embodiment,AI-assisted annotation 1310 (e.g., implemented using an AI-assistedannotation SDK) may leverage machine learning models (e.g., neuralnetworks) to generate suggested or predicted ground truth data for acustomer dataset. In at least one embodiment, user 1510 may useannotation tools within a user interface (a graphical user interface(GUI)) on computing device 1508.

In at least one embodiment, user 1510 may interact with a GUI viacomputing device 1508 to edit or fine-tune (auto)annotations. In atleast one embodiment, a polygon editing feature may be used to movevertices of a polygon to more accurate or fine-tuned locations.

In at least one embodiment, once customer dataset 1506 has associatedground truth data, ground truth data (e.g., from AI-assisted annotation,manual labeling, etc.) may be used by during model training 1314 togenerate refined model 1512. In at least one embodiment, customerdataset 1506 may be applied to initial model 1504 any number of times,and ground truth data may be used to update parameters of initial model1504 until an acceptable level of accuracy is attained for refined model1512. In at least one embodiment, once refined model 1512 is generated,refined model 1512 may be deployed within one or more deploymentpipelines 1410 at a facility for performing one or more processing taskswith respect to medical imaging data.

In at least one embodiment, refined model 1512 may be uploaded topre-trained models 1406 in model registry 1324 to be selected by anotherfacility. In at least one embodiment, his process may be completed atany number of facilities such that refined model 1512 may be furtherrefined on new datasets any number of times to generate a more universalmodel.

FIG. 15B is an example illustration of a client-server architecture 1532to enhance annotation tools with pre-trained annotation models, inaccordance with at least one embodiment. In at least one embodiment,AI-assisted annotation tools 1536 may be instantiated based on aclient-server architecture 1532. In at least one embodiment, annotationtools 1536 in imaging applications may aid radiologists, for example,identify organs and abnormalities. In at least one embodiment, imagingapplications may include software tools that help user 1510 to identify,as a non-limiting example, a few extreme points on a particular organ ofinterest in raw images 1534 (e.g., in a 3D MRI or CT scan) and receiveauto-annotated results for all 2D slices of a particular organ. In atleast one embodiment, results may be stored in a data store as trainingdata 1538 and used as (for example and without limitation) ground truthdata for training. In at least one embodiment, when computing device1508 sends extreme points for AI-assisted annotation 1310, a deeplearning model, for example, may receive this data as input and returninference results of a segmented organ or abnormality. In at least oneembodiment, pre-instantiated annotation tools, such as AI-AssistedAnnotation Tool 1536B in FIG. 15B, may be enhanced by making API calls(e.g., API Call 1544) to a server, such as an Annotation AssistantServer 1540 that may include a set of pre-trained models 1542 stored inan annotation model registry, for example. In at least one embodiment,an annotation model registry may store pre-trained models 1542 (e.g.,machine learning models, such as deep learning models) that arepre-trained to perform AI-assisted annotation on a particular organ orabnormality. These models may be further updated by using trainingpipelines 1404. In at least one embodiment, pre-installed annotationtools may be improved over time as new labeled clinic data 1312 isadded.

Such components can be used to render images using ray tracing-basedimportance sampling, which can be accelerated through hardware.

Automated Technology

FIG. 16A is a block diagram illustrating an example system architecturefor autonomous vehicle 1600 of FIG. 16A, according to at least oneembodiment. In at least one embodiment, each of components, features,and systems of vehicle 1600 in FIG. 16A are illustrated as beingconnected via a bus 1602. In at least one embodiment, bus 1602 mayinclude, without limitation, a CAN data interface (alternativelyreferred to herein as a “CAN bus”). In at least one embodiment, a CANbus may be a network inside vehicle 1600 used to aid in control ofvarious features and functionality of vehicle 1600, such as actuation ofbrakes, acceleration, braking, steering, windshield wipers, etc. In atleast one embodiment, bus 1602 may be configured to have dozens or evenhundreds of nodes, each with its own unique identifier (e.g., a CAN ID).In at least one embodiment, bus 1602 may be read to find steering wheelangle, ground speed, engine revolutions per minute (“RPMs”), buttonpositions, and/or other vehicle status indicators. In at least oneembodiment, bus 1602 may be a CAN bus that is ASIL B compliant.

In at least one embodiment, in addition to, or alternatively from CAN,FlexRay and/or Ethernet may be used. In at least one embodiment, theremay be any number of busses 1602, which may include, without limitation,zero or more CAN busses, zero or more FlexRay busses, zero or moreEthernet busses, and/or zero or more other types of busses using adifferent protocol. In at least one embodiment, two or more busses 1602may be used to perform different functions, and/or may be used forredundancy. For example, a first bus 1602 may be used for collisionavoidance functionality and a second bus 1602 may be used for actuationcontrol. In at least one embodiment, each bus 1602 may communicate withany of components of vehicle 1600, and two or more busses 1602 maycommunicate with same components. In at least one embodiment, each ofany number of system(s) on chip(s) (“SoC(s)”) 1604, each ofcontroller(s) 1636, and/or each computer within vehicle may have accessto same input data (e.g., inputs from sensors of vehicle 1600), and maybe connected to a common bus, such CAN bus.

In at least one embodiment, vehicle 1600 may include one or morecontroller(s) 1636, such as those described herein with respect to FIG.1A. Controller(s) 1636 may be used for a variety of functions. In atleast one embodiment, controller(s) 1636 may be coupled to any ofvarious other components and systems of vehicle 1600, and may be usedfor control of vehicle 1600, artificial intelligence of vehicle 1600,infotainment for vehicle 1600, and/or like.

In at least one embodiment, vehicle 1600 may include any number of SoCs1604. Each of SoCs 1604 may include, without limitation, centralprocessing units (“CPU(s)”) 1606, graphics processing units (“GPU(s)”)1608, processor(s) 1610, cache(s) 1612, accelerator(s) 1614, datastore(s) 1616, and/or other components and features not illustrated. Inat least one embodiment, SoC(s) 1604 may be used to control vehicle 1600in a variety of platforms and systems. For example, in at least oneembodiment, SoC(s) 1604 may be combined in a system (e.g., system ofvehicle 1600) with a High Definition (“HD”) map 1622 which may obtainmap refreshes and/or updates via network interface 1624 from one or moreservers (not shown in FIG. 16A).

In at least one embodiment, CPU(s) 1606 may include a CPU cluster or CPUcomplex (alternatively referred to herein as a “CCPLEX”). In at leastone embodiment, CPU(s) 1606 may include multiple cores and/or level two(“L2”) caches. For instance, in at least one embodiment, CPU(s) 1606 mayinclude eight cores in a coherent multi-processor configuration. In atleast one embodiment, CPU(s) 1606 may include four dual-core clusterswhere each cluster has a dedicated L2 cache (e.g., a 2 MB L2 cache). Inat least one embodiment, CPU(s) 1606 (e.g., CCPLEX) may be configured tosupport simultaneous cluster operation enabling any combination ofclusters of CPU(s) 1606 to be active at any given time.

In at least one embodiment, one or more of CPU(s) 1606 may implementpower management capabilities that include, without limitation, one ormore of following features: individual hardware blocks may beclock-gated automatically when idle to save dynamic power; each coreclock may be gated when core is not actively executing instructions dueto execution of Wait for Interrupt (“WFI”)/Wait for Event (“WFE”)instructions; each core may be independently power-gated; each corecluster may be independently clock-gated when all cores are clock-gatedor power-gated; and/or each core cluster may be independentlypower-gated when all cores are power-gated. In at least one embodiment,CPU(s) 1606 may further implement an enhanced algorithm for managingpower states, where allowed power states and expected wakeup times arespecified, and hardware/microcode determines best power state to enterfor core, cluster, and CCPLEX. In at least one embodiment, processingcores may support simplified power state entry sequences in softwarewith work offloaded to microcode.

In at least one embodiment, GPU(s) 1608 may include an integrated GPU(alternatively referred to herein as an “iGPU”). In at least oneembodiment, GPU(s) 1608 may be programmable and may be efficient forparallel workloads. In at least one embodiment, GPU(s) 1608, in at leastone embodiment, may use an enhanced tensor instruction set. In at leastone embodiment, GPU(s) 1608 may include one or more streamingmicroprocessors, where each streaming microprocessor may include a levelone (“L1”) cache (e.g., an L1 cache with at least 96 KB storagecapacity), and two or more of streaming microprocessors may share an L2cache (e.g., an L2 cache with a 512 KB storage capacity). In at leastone embodiment, GPU(s) 1608 may include at least eight streamingmicroprocessors. In at least one embodiment, GPU(s) 1608 may use computeapplication programming interface(s) (API(s)). In at least oneembodiment, GPU(s) 1608 may use one or more parallel computing platformsand/or programming models (e.g., NVIDIA's CUDA).

In at least one embodiment, one or more of GPU(s) 1608 may bepower-optimized for best performance in automotive and embedded usecases. For example, in on embodiment, GPU(s) 1608 could be fabricated ona Fin field-effect transistor (“FinFET”). In at least one embodiment,each streaming microprocessor may incorporate a number ofmixed-precision processing cores partitioned into multiple blocks. Forexample, and without limitation, 64 PF32 cores and 32 PF64 cores couldbe partitioned into four processing blocks. In at least one embodiment,each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16INT32 cores, two mixed-precision NVIDIA TENSOR COREs for deep learningmatrix arithmetic, a level zero (“L0”) instruction cache, a warpscheduler, a dispatch unit, and/or a 64 KB register file. In at leastone embodiment, streaming microprocessors may include independentparallel integer and floating-point data paths to provide for efficientexecution of workloads with a mix of computation and addressingcalculations. In at least one embodiment, streaming microprocessors mayinclude independent thread scheduling capability to enable finer-grainsynchronization and cooperation between parallel threads. In at leastone embodiment, streaming microprocessors may include a combined L1 datacache and shared memory unit in order to improve performance whilesimplifying programming.

In at least one embodiment, one or more of GPU(s) 1608 may include ahigh bandwidth memory (“HBM) and/or a 16 GB HBM2 memory subsystem toprovide, in some examples, about 900 GB/second peak memory bandwidth. Inat least one embodiment, in addition to, or alternatively from, HBMmemory, a synchronous graphics random-access memory (“SGRAM”) may beused, such as a graphics double data rate type five synchronousrandom-access memory (“GDDR5”).

In at least one embodiment, GPU(s) 1608 may include unified memorytechnology. In at least one embodiment, address translation services(“ATS”) support may be used to allow GPU(s) 1608 to access CPU(s) 1606page tables directly. In at least one embodiment, embodiment, whenGPU(s) 1608 memory management unit (“MMU”) experiences a miss, anaddress translation request may be transmitted to CPU(s) 1606. Inresponse, CPU(s) 1606 may look in its page tables forvirtual-to-physical mapping for address and transmits translation backto GPU(s) 1608, in at least one embodiment. In at least one embodiment,unified memory technology may allow a single unified virtual addressspace for memory of both CPU(s) 1606 and GPU(s) 1608, therebysimplifying GPU(s) 1608 programming and porting of applications toGPU(s) 1608.

In at least one embodiment, GPU(s) 1608 may include any number of accesscounters that may keep track of frequency of access of GPU(s) 1608 tomemory of other processors. In at least one embodiment, accesscounter(s) may help ensure that memory pages are moved to physicalmemory of processor that is accessing pages most frequently, therebyimproving efficiency for memory ranges shared between processors.

In at least one embodiment, one or more of SoC(s) 1604 may include anynumber of cache(s) 1612, including those described herein. For example,in at least one embodiment, cache(s) 1612 could include a level three(“L3”) cache that is available to both CPU(s) 1606 and GPU(s) 1608(e.g., that is connected both CPU(s) 1606 and GPU(s) 1608). In at leastone embodiment, cache(s) 1612 may include a write-back cache that maykeep track of states of lines, such as by using a cache coherenceprotocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, L3cache may include 4 MB or more, depending on embodiment, althoughsmaller cache sizes may be used.

In at least one embodiment, one or more of SoC(s) 1604 may include oneor more accelerator(s) 1614 (e.g., hardware accelerators, softwareaccelerators, or a combination thereof). In at least one embodiment,SoC(s) 1604 may include a hardware acceleration cluster that may includeoptimized hardware accelerators and/or large on-chip memory. In at leastone embodiment, large on-chip memory (e.g., 4 MB of SRAM), may enablehardware acceleration cluster to accelerate neural networks and othercalculations. In at least one embodiment, hardware acceleration clustermay be used to complement GPU(s) 1608 and to off-load some of tasks ofGPU(s) 1608 (e.g., to free up more cycles of GPU(s) 1608 for performingother tasks). In at least one embodiment, accelerator(s) 1614 could beused for targeted workloads (e.g., perception, convolutional neuralnetworks (“CNNs”), recurrent neural networks (“RNNs”), etc.) that arestable enough to be amenable to acceleration. In at least oneembodiment, a CNN may include a region-based or regional convolutionalneural networks (“RCNNs”) and Fast RCNNs (e.g., as used for objectdetection) or other type of CNN.

In at least one embodiment, accelerator(s) 1614 (e.g., hardwareacceleration cluster) may include a deep learning accelerator(s)(“DLA(s)”). DLA(s) may include, without limitation, one or more Tensorprocessing units (“TPU(s)”) that may be configured to provide anadditional ten trillion operations per second for deep learningapplications and inferencing. In at least one embodiment, TPU(s) may beaccelerators configured to, and optimized for, performing imageprocessing functions (e.g., for CNNs, RCNNs, etc.). DLA(s) may furtherbe optimized for a specific set of neural network types and floatingpoint operations, as well as inferencing. In at least one embodiment,design of DLA(s) may provide more performance per millimeter than atypical general-purpose GPU, and typically vastly exceeds performance ofa CPU. In at least one embodiment, TPU(s) may perform several functions,including a single-instance convolution function, supporting, forexample, INT8, INT16, and FP16 data types for both features and weights,as well as post-processor functions. In at least one embodiment, DLA(s)may quickly and efficiently execute neural networks, especially CNNs, onprocessed or unprocessed data for any of a variety of functions,including, for example and without limitation: a CNN for objectidentification and detection using data from camera sensors; a CNN fordistance estimation using data from camera sensors; a CNN for emergencyvehicle detection and identification and detection using data frommicrophones 1696; a CNN for facial recognition and vehicle owneridentification using data from camera sensors; and/or a CNN for securityand/or safety related events.

In at least one embodiment, DLA(s) may perform any function of GPU(s)1608, and by using an inference accelerator, for example, a designer maytarget either DLA(s) or GPU(s) 1608 for any function. For example, in atleast one embodiment, designer may focus processing of CNNs and floatingpoint operations on DLA(s) and leave other functions to GPU(s) 1608and/or other accelerator(s) 1614.

In at least one embodiment, accelerator(s) 1614 (e.g., hardwareacceleration cluster) may include a programmable vision accelerator(s)(“PVA”), which may alternatively be referred to herein as a computervision accelerator. In at least one embodiment, PVA(s) may be designedand configured to accelerate computer vision algorithms for advanceddriver assistance system (“ADAS”) 1638, autonomous driving, augmentedreality (“AR”) applications, and/or virtual reality (“VR”) applications.PVA(s) may provide a balance between performance and flexibility. Forexample, in at least one embodiment, each PVA(s) may include, forexample and without limitation, any number of reduced instruction setcomputer (“RISC”) cores, direct memory access (“DMA”), and/or any numberof vector processors.

In at least one embodiment, RISC cores may interact with image sensors(e.g., image sensors of any of cameras described herein), image signalprocessor(s), and/or like. In at least one embodiment, each of RISCcores may include any amount of memory. In at least one embodiment, RISCcores may use any of a number of protocols, depending on embodiment. Inat least one embodiment, RISC cores may execute a real-time operatingsystem (“RTOS”). In at least one embodiment, RISC cores may beimplemented using one or more integrated circuit devices, applicationspecific integrated circuits (“ASICs”), and/or memory devices. Forexample, in at least one embodiment, RISC cores could include aninstruction cache and/or a tightly coupled RAM.

In at least one embodiment, DMA may enable components of PVA(s) toaccess system memory independently of CPU(s) 1606. In at least oneembodiment, DMA may support any number of features used to provideoptimization to PVA including, but not limited to, supportingmulti-dimensional addressing and/or circular addressing. In at least oneembodiment, DMA may support up to six or more dimensions of addressing,which may include, without limitation, block width, block height, blockdepth, horizontal block stepping, vertical block stepping, and/or depthstepping.

In at least one embodiment, vector processors may be programmableprocessors that may be designed to efficiently and flexibly executeprogramming for computer vision algorithms and provide signal processingcapabilities. In at least one embodiment, PVA may include a PVA core andtwo vector processing subsystem partitions. In at least one embodiment,PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMAengines), and/or other peripherals. In at least one embodiment, vectorprocessing subsystem may operate as primary processing engine of PVA,and may include a vector processing unit (“VPU”), an instruction cache,and/or vector memory (e.g., “VMEM”). In at least one embodiment, VPU mayinclude a digital signal processor such as, for example, a singleinstruction, multiple data (“SIMD”), very long instruction word (“VLIW”)digital signal processor. In at least one embodiment, a combination ofSEID and VLIW may enhance throughput and speed.

In at least one embodiment, each of vector processors may include aninstruction cache and may be coupled to dedicated memory. As a result,in at least one embodiment, each of vector processors may be configuredto execute independently of other vector processors. In at least oneembodiment, vector processors that are included in a particular PVA maybe configured to employ data parallelism. For instance, in at least oneembodiment, plurality of vector processors included in a single PVA mayexecute same computer vision algorithm, but on different regions of animage. In at least one embodiment, vector processors included in aparticular PVA may simultaneously execute different computer visionalgorithms, on same image, or even execute different algorithms onsequential images or portions of an image. In at least one embodiment,among other things, any number of PVAs may be included in hardwareacceleration cluster and any number of vector processors may be includedin each of PVAs. In at least one embodiment, PVA(s) may includeadditional error correcting code (“ECC”) memory, to enhance overallsystem safety.

In at least one embodiment, accelerator(s) 1614 (e.g., hardwareacceleration cluster) may include a computer vision network on-chip andstatic random-access memory (“SRAM”), for providing a high-bandwidth,low latency SRAM for accelerator(s) 1614. In at least one embodiment,on-chip memory may include at least 4 MB SRAM, consisting of, forexample and without limitation, eight field-configurable memory blocks,that may be accessible by both PVA and DLA. In at least one embodiment,each pair of memory blocks may include an advanced peripheral bus(“APB”) interface, configuration circuitry, a controller, and amultiplexer. In at least one embodiment, any type of memory may be used.In at least one embodiment, PVA and DLA may access memory via a backbonethat provides PVA and DLA with high-speed access to memory. In at leastone embodiment, backbone may include a computer vision network on-chipthat interconnects PVA and DLA to memory (e.g., using APB).

In at least one embodiment, computer vision network on-chip may includean interface that determines, before transmission of any controlsignal/address/data, that both PVA and DLA provide ready and validsignals. In at least one embodiment, an interface may provide forseparate phases and separate channels for transmitting controlsignals/addresses/data, as well as burst-type communications forcontinuous data transfer. In at least one embodiment, an interface maycomply with International Organization for Standardization (“ISO”) 26262or International Electrotechnical Commission (“IEC”) 61508 standards,although other standards and protocols may be used.

In at least one embodiment, one or more of SoC(s) 1604 may include areal-time ray-tracing hardware accelerator. In at least one embodiment,real-time ray-tracing hardware accelerator may be used to quickly andefficiently determine positions and extents of objects (e.g., within aworld model), to generate real-time visualization simulations, for RADARsignal interpretation, for sound propagation synthesis and/or analysis,for simulation of SONAR systems, for general wave propagationsimulation, for comparison to LIDAR data for purposes of localizationand/or other functions, and/or for other uses.

In at least one embodiment, accelerator(s) 1614 (e.g., hardwareaccelerator cluster) have a wide array of uses for autonomous driving.In at least one embodiment, PVA may be a programmable vision acceleratorthat may be used for key processing stages in ADAS and autonomousvehicles. In at least one embodiment, PVA's capabilities are a goodmatch for algorithmic domains needing predictable processing, at lowpower and low latency. In other words, PVA performs well on semi-denseor dense regular computation, even on small data sets, which needpredictable run-times with low latency and low power. In at least oneembodiment, autonomous vehicles, such as vehicle 1600, PVAs are designedto run classic computer vision algorithms, as they are efficient atobject detection and operating on integer math.

For example, according to at least one embodiment of technology, PVA isused to perform computer stereo vision. In at least one embodiment,semi-global matching-based algorithm may be used in some examples,although this is not intended to be limiting. In at least oneembodiment, applications for Level 3-5 autonomous driving use motionestimation/stereo matching on-the-fly (e.g., structure from motion,pedestrian recognition, lane detection, etc.). In at least oneembodiment, PVA may perform computer stereo vision function on inputsfrom two monocular cameras.

In at least one embodiment, PVA may be used to perform dense opticalflow. For example, in at least one embodiment, PVA could process rawRADAR data (e.g., using a 4D Fast Fourier Transform) to provideprocessed RADAR data. In at least one embodiment, PVA is used for timeof flight depth processing, by processing raw time of flight data toprovide processed time of flight data, for example.

In at least one embodiment, DLA may be used to run any type of networkto enhance control and driving safety, including for example and withoutlimitation, a neural network that outputs a measure of confidence foreach object detection. In at least one embodiment, confidence may berepresented or interpreted as a probability, or as providing a relative“weight” of each detection compared to other detections. In at least oneembodiment, confidence enables a system to make further decisionsregarding which detections should be considered as true positivedetections rather than false positive detections. For example, In atleast one embodiment, a system may set a threshold value for confidenceand consider only detections exceeding threshold value as true positivedetections. In an embodiment in which an automatic emergency braking(“AEB”) system is used, false positive detections would cause vehicle toautomatically perform emergency braking, which is obviously undesirable.In at least one embodiment, highly confident detections may beconsidered as triggers for AEB. In at least one embodiment, DLA may runa neural network for regressing confidence value. In at least oneembodiment, neural network may take as its input at least some subset ofparameters, such as bounding box dimensions, ground plane estimateobtained (e.g. from another subsystem), output from IU sensor(s) 1666that correlates with vehicle 1600 orientation, distance, 3D locationestimates of object obtained from neural network and/or other sensors(e.g., LIDAR sensor(s) 1664 or RADAR sensor(s) 1660), among others.

In at least one embodiment, one or more of SoC(s) 1604 may include datastore(s) 1616 (e.g., memory). In at least one embodiment, data store(s)1616 may be on-chip memory of SoC(s) 1604, which may store neuralnetworks to be executed on GPU(s) 1608 and/or DLA. In at least oneembodiment, data store(s) 1616 may be large enough in capacity to storemultiple instances of neural networks for redundancy and safety. In atleast one embodiment, data store(s) 1616 may comprise L2 or L3 cache(s).

In at least one embodiment, one or more of SoC(s) 1604 may include anynumber of processor(s) 1610 (e.g., embedded processors). In at least oneembodiment, processor(s) 1610 may include a boot and power managementprocessor that may be a dedicated processor and subsystem to handle bootpower and management functions and related security enforcement. In atleast one embodiment, boot and power management processor may be a partof SoC(s) 1604 boot sequence and may provide runtime power managementservices. In at least one embodiment, boot power and managementprocessor may provide clock and voltage programming, assistance insystem low power state transitions, management of SoC(s) 1604 thermalsand temperature sensors, and/or management of SoC(s) 1604 power states.In at least one embodiment, each temperature sensor may be implementedas a ring-oscillator whose output frequency is proportional totemperature, and SoC(s) 1604 may use ring-oscillators to detecttemperatures of CPU(s) 1606, GPU(s) 1608, and/or accelerator(s) 1614. Inat least one embodiment, if temperatures are determined to exceed athreshold, then boot and power management processor may enter atemperature fault routine and put SoC(s) 1604 into a lower power stateand/or put vehicle 1600 into a chauffeur to safe stop mode (e.g., bringvehicle 1600 to a safe stop).

In at least one embodiment, processor(s) 1610 may further include a setof embedded processors that may serve as an audio processing engine. Inat least one embodiment, audio processing engine may be an audiosubsystem that enables full hardware support for multi-channel audioover multiple interfaces, and a broad and flexible range of audio I/Ointerfaces. In at least one embodiment, audio processing engine is adedicated processor core with a digital signal processor with dedicatedRAM.

In at least one embodiment, processor(s) 1610 may further include analways on processor engine that may provide necessary hardware featuresto support low power sensor management and wake use cases. In at leastone embodiment, always on processor engine may include, withoutlimitation, a processor core, a tightly coupled RAM, supportingperipherals (e.g., timers and interrupt controllers), various I/Ocontroller peripherals, and routing logic.

In at least one embodiment, processor(s) 1610 may further include asafety cluster engine that includes, without limitation, a dedicatedprocessor subsystem to handle safety management for automotiveapplications. In at least one embodiment, safety cluster engine mayinclude, without limitation, two or more processor cores, a tightlycoupled RAM, support peripherals (e.g., timers, an interrupt controller,etc.), and/or routing logic. In a safety mode, two or more cores mayoperate, in at least one embodiment, in a lockstep mode and function asa single core with comparison logic to detect any differences betweentheir operations. In at least one embodiment, processor(s) 1610 mayfurther include a real-time camera engine that may include, withoutlimitation, a dedicated processor subsystem for handling real-timecamera management. In at least one embodiment, processor(s) 1610 mayfurther include a high-dynamic range signal processor that may include,without limitation, an image signal processor that is a hardware enginethat is part of camera processing pipeline.

In at least one embodiment, processor(s) 1610 may include a video imagecompositor that may be a processing block (e.g., implemented on amicroprocessor) that implements video post-processing functions neededby a video playback application to produce final image for playerwindow. In at least one embodiment, video image compositor may performlens distortion correction on wide-view camera(s) 1670, surroundcamera(s) 1674, and/or on in-cabin monitoring camera sensor(s). In atleast one embodiment, in-cabin monitoring camera sensor(s) arepreferably monitored by a neural network running on another instance ofSoC(s) 1604, configured to identify in cabin events and respondaccordingly. In at least one embodiment, an in-cabin system may perform,without limitation, lip reading to activate cellular service and place aphone call, dictate emails, change vehicle's destination, activate orchange vehicle's infotainment system and settings, or providevoice-activated web surfing. In at least one embodiment, certainfunctions are available to driver when vehicle is operating in anautonomous mode and are disabled otherwise.

In at least one embodiment, video image compositor may include enhancedtemporal noise reduction for both spatial and temporal noise reduction.For example, in at least one embodiment, where motion occurs in a video,noise reduction weights spatial information appropriately, decreasingweight of information provided by adjacent frames. In at least oneembodiment, where an image or portion of an image does not includemotion, temporal noise reduction performed by video image compositor mayuse information from previous image to reduce noise in current image.

In at least one embodiment, video image compositor may also beconfigured to perform stereo rectification on input stereo lens frames.In at least one embodiment, video image compositor may further be usedfor user interface composition when operating system desktop is in use,and GPU(s) 1608 are not required to continuously render new surfaces. Inat least one embodiment, when GPU(s) 1608 are powered on and activedoing 3D rendering, video image compositor may be used to offload GPU(s)1608 to improve performance and responsiveness.

In at least one embodiment, one or more of SoC(s) 1604 may furtherinclude a mobile industry processor interface (“MIPI”) camera serialinterface for receiving video and input from cameras, a high-speedinterface, and/or a video input block that may be used for camera andrelated pixel input functions. In at least one embodiment, one or moreof SoC(s) 1604 may further include an input/output controller(s) thatmay be controlled by software and may be used for receiving I/O signalsthat are uncommitted to a specific role.

In at least one embodiment, one or more of SoC(s) 1604 may furtherinclude a broad range of peripheral interfaces to enable communicationwith peripherals, audio encoders/decoders (“codecs”), power management,and/or other devices. SoC(s) 1604 may be used to process data fromcameras (e.g., connected over Gigabit Multimedia Serial Link andEthernet), sensors (e.g., LIDAR sensor(s) 1664, RADAR sensor(s) 1660,etc. that may be connected over Ethernet), data from bus 1602 (e.g.,speed of vehicle 1600, steering wheel position, etc.), data from GNSSsensor(s) 1658 (e.g., connected over Ethernet or CAN bus), etc. In atleast one embodiment, one or more of SoC(s) 1604 may further includededicated high-performance mass storage controllers that may includetheir own DMA engines, and that may be used to free CPU(s) 1606 fromroutine data management tasks.

In at least one embodiment, SoC(s) 1604 may be an end-to-end platformwith a flexible architecture that spans automation levels 3-5, therebyproviding a comprehensive functional safety architecture that leveragesand makes efficient use of computer vision and ADAS techniques fordiversity and redundancy, provides a platform for a flexible, reliabledriving software stack, along with deep learning tools. In at least oneembodiment, SoC(s) 1604 may be faster, more reliable, and even moreenergy-efficient and space-efficient than conventional systems. Forexample, in at least one embodiment, accelerator(s) 1614, when combinedwith CPU(s) 1606, GPU(s) 1608, and data store(s) 1616, may provide for afast, efficient platform for level 3-5 autonomous vehicles.

In at least one embodiment, computer vision algorithms may be executedon CPUs, which may be configured using high-level programming language,such as C programming language, to execute a wide variety of processingalgorithms across a wide variety of visual data. However, in at leastone embodiment, CPUs are oftentimes unable to meet performancerequirements of many computer vision applications, such as those relatedto execution time and power consumption, for example. In at least oneembodiment, many CPUs are unable to execute complex object detectionalgorithms in real-time, which is used in in-vehicle ADAS applicationsand in practical Level 3-5 autonomous vehicles.

Embodiments described herein allow for multiple neural networks to beperformed simultaneously and/or sequentially, and for results to becombined together to enable Level 3-5 autonomous driving functionality.For example, in at least one embodiment, a CNN executing on DLA ordiscrete GPU (e.g., GPU(s) 1620) may include text and word recognition,allowing supercomputer to read and understand traffic signs, includingsigns for which neural network has not been specifically trained. In atleast one embodiment, DLA may further include a neural network that isable to identify, interpret, and provide semantic understanding of sign,and to pass that semantic understanding to path planning modules runningon CPU Complex.

In at least one embodiment, multiple neural networks may be runsimultaneously, as for Level 3, 4, or 5 driving. For example, in atleast one embodiment, a warning sign consisting of “Caution: flashinglights indicate icy conditions,” along with an electric light, may beindependently or collectively interpreted by several neural networks. Inat least one embodiment, a sign itself may be identified as a trafficsign by a first deployed neural network (e.g., a neural network that hasbeen trained) and a text “flashing lights indicate icy conditions” maybe interpreted by a second deployed neural network, which informsvehicle's path planning software (preferably executing on CPU Complex)that when flashing lights are detected, icy conditions exist. In atleast one embodiment, a flashing light may be identified by operating athird deployed neural network over multiple frames, informing vehicle'spath-planning software of presence (or absence) of flashing lights. Inat least one embodiment, all three neural networks may runsimultaneously, such as within DLA and/or on GPU(s) 1608.

In at least one embodiment, a CNN for facial recognition and vehicleowner identification may use data from camera sensors to identifypresence of an authorized driver and/or owner of vehicle 1600. In atleast one embodiment, an always on sensor processing engine may be usedto unlock vehicle when owner approaches driver door and turn on lights,and, in security mode, to disable vehicle when owner leaves vehicle. Inthis way, SoC(s) 1604 provide for security against theft and/orcarjacking.

In at least one embodiment, a CNN for emergency vehicle detection andidentification may use data from microphones 1696 to detect and identifyemergency vehicle sirens. In at least one embodiment, SoC(s) 1604 useCNN for classifying environmental and urban sounds, as well asclassifying visual data. In at least one embodiment, CNN running on DLAis trained to identify relative closing speed of emergency vehicle(e.g., by using Doppler effect). In at least one embodiment, CNN mayalso be trained to identify emergency vehicles specific to local area inwhich vehicle is operating, as identified by GNSS sensor(s) 1658. In atleast one embodiment, when operating in Europe, CNN will seek to detectEuropean sirens, and when in United States CNN will seek to identifyonly North American sirens. In at least one embodiment, once anemergency vehicle is detected, a control program may be used to executean emergency vehicle safety routine, slowing vehicle, pulling over toside of road, parking vehicle, and/or idling vehicle, with assistance ofultrasonic sensor(s) 1662, until emergency vehicle(s) passes.

In at least one embodiment, vehicle 1600 may include CPU(s) 1618 (e.g.,discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s) 1604 via ahigh-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s)1618 may include an X86 processor, for example. CPU(s) 1618 may be usedto perform any of a variety of functions, including arbitratingpotentially inconsistent results between ADAS sensors and SoC(s) 1604,and/or monitoring status and health of controller(s) 1636 and/or aninfotainment system on a chip (“infotainment SoC”) 1630, for example.

In at least one embodiment, vehicle 1600 may include GPU(s) 1620 (e.g.,discrete GPU(s), or dGPU(s)), that may be coupled to SoC(s) 1604 via ahigh-speed interconnect (e.g., NVIDIA's NVLINK). In at least oneembodiment, GPU(s) 1620 may provide additional artificial intelligencefunctionality, such as by executing redundant and/or different neuralnetworks, and may be used to train and/or update neural networks basedat least in part on input (e.g., sensor data) from sensors of vehicle1600.

In at least one embodiment, vehicle 1600 may further include networkinterface 1624 which may include, without limitation, wirelessantenna(s) 1626 (e.g., one or more wireless antennas 1626 for differentcommunication protocols, such as a cellular antenna, a Bluetoothantenna, etc.). In at least one embodiment, network interface 1624 maybe used to enable wireless connectivity over Internet with cloud (e.g.,with server(s) and/or other network devices), with other vehicles,and/or with computing devices (e.g., client devices of passengers). Inat least one embodiment, to communicate with other vehicles, a directlink may be established between vehicle 160 and other vehicle and/or anindirect link may be established (e.g., across networks and overInternet). In at least one embodiment, direct links may be providedusing a vehicle-to-vehicle communication link. A vehicle-to-vehiclecommunication link may provide vehicle 1600 information about vehiclesin proximity to vehicle 1600 (e.g., vehicles in front of, on side of,and/or behind vehicle 1600). In at least one embodiment, aforementionedfunctionality may be part of a cooperative adaptive cruise controlfunctionality of vehicle 1600.

In at least one embodiment, network interface 1624 may include an SoCthat provides modulation and demodulation functionality and enablescontroller(s) 1636 to communicate over wireless networks. In at leastone embodiment, network interface 1624 may include a radio frequencyfront-end for up-conversion from baseband to radio frequency, and downconversion from radio frequency to baseband. In at least one embodiment,frequency conversions may be performed in any technically feasiblefashion. For example, frequency conversions could be performed throughwell-known processes, and/or using super-heterodyne processes. In atleast one embodiment, radio frequency front end functionality may beprovided by a separate chip. In at least one embodiment, networkinterface may include wireless functionality for communicating over LTE,WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave,ZigBee, LoRaWAN, and/or other wireless protocols.

In at least one embodiment, vehicle 1600 may further include datastore(s) 1628 which may include, without limitation, off-chip (e.g., offSoC(s) 1604) storage. In at least one embodiment, data store(s) 1628 mayinclude, without limitation, one or more storage elements including RAM,SRAM, dynamic random-access memory (“DRAM”), video random-access memory(“VRAM”), Flash, hard disks, and/or other components and/or devices thatmay store at least one bit of data.

In at least one embodiment, vehicle 1600 may further include GNSSsensor(s) 1658 (e.g., GPS and/or assisted GPS sensors), to assist inmapping, perception, occupancy grid generation, and/or path planningfunctions. In at least one embodiment, any number of GNSS sensor(s) 1658may be used, including, for example and without limitation, a GPS usinga USB connector with an Ethernet to Serial (e.g., RS-232) bridge.

In at least one embodiment, vehicle 1600 may further include RADARsensor(s) 1660. RADAR sensor(s) 1660 may be used by vehicle 1600 forlong-range vehicle detection, even in darkness and/or severe weatherconditions. In at least one embodiment, RADAR functional safety levelsmay be ASIL B. RADAR sensor(s) 1660 may use CAN and/or bus 1602 (e.g.,to transmit data generated by RADAR sensor(s) 1660) for control and toaccess object tracking data, with access to Ethernet to access raw datain some examples. In at least one embodiment, wide variety of RADARsensor types may be used. For example, and without limitation, RADARsensor(s) 1660 may be suitable for front, rear, and side RADAR use. Inat least one embodiment, one or more of RADAR sensors(s) 1660 are PulseDoppler RADAR sensor(s).

In at least one embodiment, RADAR sensor(s) 1660 may include differentconfigurations, such as long-range with narrow field of view,short-range with wide field of view, short-range side coverage, etc. Inat least one embodiment, long-range RADAR may be used for adaptivecruise control functionality. In at least one embodiment, long-rangeRADAR systems may provide a broad field of view realized by two or moreindependent scans, such as within a 250 m range. In at least oneembodiment, RADAR sensor(s) 1660 may help in distinguishing betweenstatic and moving objects, and may be used by ADAS system 1638 foremergency brake assist and forward collision warning. Sensors 1660(s)included in a long-range RADAR system may include, without limitation,monostatic multimodal RADAR with multiple (e.g., six or more) fixedRADAR antennae and a high-speed CAN and FlexRay interface. In at leastone embodiment, with six antennae, central four antennae may create afocused beam pattern, designed to record vehicle 1600's surroundings athigher speeds with minimal interference from traffic in adjacent lanes.In at least one embodiment, other two antennae may expand field of view,making it possible to quickly detect vehicles entering or leavingvehicle 1600's lane.

In at least one embodiment, mid-range RADAR systems may include, as anexample, a range of up to 160 m (front) or 80 m (rear), and a field ofview of up to 42 degrees (front) or 150 degrees (rear). In at least oneembodiment, short-range RADAR systems may include, without limitation,any number of RADAR sensor(s) 1660 designed to be installed at both endsof rear bumper. When installed at both ends of rear bumper, in at leastone embodiment, a RADAR sensor system may create two beams thatconstantly monitor blind spot in rear and next to vehicle. In at leastone embodiment, short-range RADAR systems may be used in ADAS system1638 for blind spot detection and/or lane change assist.

In at least one embodiment, vehicle 1600 may further include ultrasonicsensor(s) 1662. Ultrasonic sensor(s) 1662, which may be positioned atfront, back, and/or sides of vehicle 1600, may be used for park assistand/or to create and update an occupancy grid. In at least oneembodiment, a wide variety of ultrasonic sensor(s) 1662 may be used, anddifferent ultrasonic sensor(s) 1662 may be used for different ranges ofdetection (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonicsensor(s) 1662 may operate at functional safety levels of ASIL B.

In at least one embodiment, vehicle 1600 may include LIDAR sensor(s)1664. LIDAR sensor(s) 1664 may be used for object and pedestriandetection, emergency braking, collision avoidance, and/or otherfunctions. In at least one embodiment, LIDAR sensor(s) 1664 may befunctional safety level ASIL B. In at least one embodiment, vehicle 1600may include multiple LIDAR sensors 1664 (e.g., two, four, six, etc.)that may use Ethernet (e.g., to provide data to a Gigabit Ethernetswitch).

In at least one embodiment, LIDAR sensor(s) 1664 may be capable ofproviding a list of objects and their distances for a 360-degree fieldof view. In at least one embodiment, commercially available LIDARsensor(s) 1664 may have an advertised range of approximately 100 m, withan accuracy of 2 cm-3 cm, and with support for a 100 Mbps Ethernetconnection, for example. In at least one embodiment, one or morenon-protruding LIDAR sensors 1664 may be used. In such an embodiment,LIDAR sensor(s) 1664 may be implemented as a small device that may beembedded into front, rear, sides, and/or corners of vehicle 1600. In atleast one embodiment, LIDAR sensor(s) 1664, in such an embodiment, mayprovide up to a 120-degree horizontal and 35-degree verticalfield-of-view, with a 200 m range even for low-reflectivity objects. Inat least one embodiment, front-mounted LIDAR sensor(s) 1664 may beconfigured for a horizontal field of view between 45 degrees and 135degrees.

In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR,may also be used. 3D Flash LIDAR uses a flash of a laser as atransmission source, to illuminate surroundings of vehicle 1600 up toapproximately 200 m. In at least one embodiment, a flash LIDAR unitincludes, without limitation, a receptor, which records laser pulsetransit time and reflected light on each pixel, which in turncorresponds to range from vehicle 1600 to objects. In at least oneembodiment, flash LIDAR may allow for highly accurate anddistortion-free images of surroundings to be generated with every laserflash. In at least one embodiment, four flash LIDAR sensors may bedeployed, one at each side of vehicle 1600. In at least one embodiment,3D flash LIDAR systems include, without limitation, a solid-state 3Dstaring array LIDAR camera with no moving parts other than a fan (e.g.,a non-scanning LIDAR device). In at least one embodiment, flash LIDARdevice(s) may use a 5 nanosecond class I (eye-safe) laser pulse perframe and may capture reflected laser light in form of 3D range pointclouds and co-registered intensity data.

In at least one embodiment, vehicle may further include IU sensor(s)1666. In at least one embodiment, IMU sensor(s) 1666 may be located at acenter of rear axle of vehicle 1600, in at least one embodiment. In atleast one embodiment, IMU sensor(s) 1666 may include, for example andwithout limitation, accelerometer(s), magnetometer(s), gyroscope(s),magnetic compass(es), and/or other sensor types. In at least oneembodiment, such as in six-axis applications, IMU sensor(s) 1666 mayinclude, without limitation, accelerometers and gyroscopes. In at leastone embodiment, such as in nine-axis applications, IU sensor(s) 1666 mayinclude, without limitation, accelerometers, gyroscopes, andmagnetometers.

In at least one embodiment, IU sensor(s) 1666 may be implemented as aminiature, high performance GPS-Aided Inertial Navigation System(“GPS/INS”) that combines micro-electro-mechanical systems (“MEMS”)inertial sensors, a high-sensitivity GPS receiver, and advanced Kalmanfiltering algorithms to provide estimates of position, velocity, andattitude. In at least one embodiment, IMU sensor(s) 1666 may enablevehicle 1600 to estimate heading without requiring input from a magneticsensor by directly observing and correlating changes in velocity fromGPS to IMU sensor(s) 1666. In at least one embodiment, IMU sensor(s)1666 and GNSS sensor(s) 1658 may be combined in a single integratedunit.

In at least one embodiment, vehicle 1600 may include microphone(s) 1696placed in and/or around vehicle 1600. In at least one embodiment,microphone(s) 1696 may be used for emergency vehicle detection andidentification, among other things.

In at least one embodiment, vehicle 1600 may further include any numberof camera types, including stereo camera(s) 1668, wide-view camera(s)1670, infrared camera(s) 1672, surround camera(s) 1674, long-rangecamera(s) 1698, mid-range camera(s) 1676, and/or other camera types. Inat least one embodiment, cameras may be used to capture image dataaround an entire periphery of vehicle 1600. In at least one embodiment,types of cameras used depends on vehicle 1600. In at least oneembodiment, any combination of camera types may be used to providenecessary coverage around vehicle 1600. In at least one embodiment,number of cameras may differ depending on embodiment. For example, in atleast one embodiment, vehicle 1600 could include six cameras, sevencameras, ten cameras, twelve cameras, or another number of cameras.Cameras may support, as an example and without limitation, GigabitMultimedia Serial Link (“GMSL”) and/or Gigabit Ethernet. In at least oneembodiment, each of camera(s) is described with more detail previouslyherein with respect to FIG. 16A and FIG. 16B.

In at least one embodiment, vehicle 1600 may further include vibrationsensor(s) 1642. In at least one embodiment, vibration sensor(s) 1642 maymeasure vibrations of components of vehicle 1600, such as axle(s). Forexample, in at least one embodiment, changes in vibrations may indicatea change in road surfaces. In at least one embodiment, when two or morevibration sensors 1642 are used, differences between vibrations may beused to determine friction or slippage of road surface (e.g., whendifference in vibration is between a power-driven axle and a freelyrotating axle).

In at least one embodiment, vehicle 1600 may include ADAS system 1638.ADAS system 1638 may include, without limitation, an SoC, in someexamples. In at least one embodiment, ADAS system 1638 may include,without limitation, any number and combination of anautonomous/adaptive/automatic cruise control (“ACC”) system, acooperative adaptive cruise control (“CACC”) system, a forward crashwarning (“FCW”) system, an automatic emergency braking (“AEB”) system, alane departure warning (“LDW)” system, a lane keep assist (“LKA”)system, a blind spot warning (“BSW”) system, a rear cross-trafficwarning (“RCTW”) system, a collision warning (“CW”) system, a lanecentering (“LC”) system, and/or other systems, features, and/orfunctionality.

In at least one embodiment, ACC system may use RADAR sensor(s) 1660,LIDAR sensor(s) 1664, and/or any number of camera(s). In at least oneembodiment, ACC system may include a longitudinal ACC system and/or alateral ACC system. In at least one embodiment, longitudinal ACC systemmonitors and controls distance to vehicle immediately ahead of vehicle1600 and automatically adjust speed of vehicle 1600 to maintain a safedistance from vehicles ahead. In at least one embodiment, lateral ACCsystem performs distance keeping, and advises vehicle 1600 to changelanes when necessary. In at least one embodiment, lateral ACC is relatedto other ADAS applications such as LC and CW.

In at least one embodiment, CACC system uses information from othervehicles that may be received via network interface 1624 and/or wirelessantenna(s) 1626 from other vehicles via a wireless link, or indirectly,over a network connection (e.g., over Internet). In at least oneembodiment, direct links may be provided by a vehicle-to-vehicle (“V2V”)communication link, while indirect links may be provided by aninfrastructure-to-vehicle (“12V”) communication link. In general, V2Vcommunication concept provides information about immediately precedingvehicles (e.g., vehicles immediately ahead of and in same lane asvehicle 1600), while I2V communication concept provides informationabout traffic further ahead. In at least one embodiment, CACC system mayinclude either or both I2V and V2V information sources. In at least oneembodiment, given information of vehicles ahead of vehicle 1600, CACCsystem may be more reliable and it has potential to improve traffic flowsmoothness and reduce congestion on road.

In at least one embodiment, FCW system is designed to alert driver to ahazard, so that driver may take corrective action. In at least oneembodiment, FCW system uses a front-facing camera and/or RADAR sensor(s)1660, coupled to a dedicated processor, DSP, FPGA, and/or ASIC, that iselectrically coupled to driver feedback, such as a display, speaker,and/or vibrating component. In at least one embodiment, FCW system mayprovide a warning, such as in form of a sound, visual warning, vibrationand/or a quick brake pulse.

In at least one embodiment, AEB system detects an impending forwardcollision with another vehicle or other object, and may automaticallyapply brakes if driver does not take corrective action within aspecified time or distance parameter. In at least one embodiment, AEBsystem may use front-facing camera(s) and/or RADAR sensor(s) 1660,coupled to a dedicated processor, DSP, FPGA, and/or ASIC. In at leastone embodiment, when AEB system detects a hazard, AEB system typicallyfirst alerts driver to take corrective action to avoid collision and, ifdriver does not take corrective action, AEB system may automaticallyapply brakes in an effort to prevent, or at least mitigate, impact ofpredicted collision. In at least one embodiment, AEB system, may includetechniques such as dynamic brake support and/or crash imminent braking.

In at least one embodiment, LDW system provides visual, audible, and/ortactile warnings, such as steering wheel or seat vibrations, to alertdriver when vehicle 1600 crosses lane markings. In at least oneembodiment, LDW system does not activate when driver indicates anintentional lane departure, by activating a turn signal. In at least oneembodiment, LDW system may use front-side facing cameras, coupled to adedicated processor, DSP, FPGA, and/or ASIC, that is electricallycoupled to driver feedback, such as a display, speaker, and/or vibratingcomponent. In at least one embodiment, LKA system is a variation of LDWsystem. LKA system provides steering input or braking to correct vehicle1600 if vehicle 1600 starts to exit lane.

In at least one embodiment, BSW system detects and warns driver ofvehicles in an automobile's blind spot. In at least one embodiment, BSWsystem may provide a visual, audible, and/or tactile alert to indicatethat merging or changing lanes is unsafe. In at least one embodiment,BSW system may provide an additional warning when driver uses a turnsignal. In at least one embodiment, BSW system may use rear-side facingcamera(s) and/or RADAR sensor(s) 1660, coupled to a dedicated processor,DSP, FPGA, and/or ASIC, that is electrically coupled to driver feedback,such as a display, speaker, and/or vibrating component.

In at least one embodiment, RCTW system may provide visual, audible,and/or tactile notification when an object is detected outsiderear-camera range when vehicle 1600 is backing up. In at least oneembodiment, RCTW system includes AEB system to ensure that vehiclebrakes are applied to avoid a crash. In at least one embodiment, RCTWsystem may use one or more rear-facing RADAR sensor(s) 1660, coupled toa dedicated processor, DSP, FPGA, and/or ASIC, that is electricallycoupled to driver feedback, such as a display, speaker, and/or vibratingcomponent.

In at least one embodiment, conventional ADAS systems may be prone tofalse positive results which may be annoying and distracting to adriver, but typically are not catastrophic, because conventional ADASsystems alert driver and allow driver to decide whether a safetycondition truly exists and act accordingly. In at least one embodiment,vehicle 1600 itself decides, in case of conflicting results, whether toheed result from a primary computer or a secondary computer (e.g., firstcontroller 1636 or second controller 1636). For example, in at least oneembodiment, ADAS system 1638 may be a backup and/or secondary computerfor providing perception information to a backup computer rationalitymodule. In at least one embodiment, backup computer rationality monitormay run a redundant diverse software on hardware components to detectfaults in perception and dynamic driving tasks. In at least oneembodiment, outputs from ADAS system 1638 may be provided to asupervisory MCU. In at least one embodiment, if outputs from primarycomputer and secondary computer conflict, supervisory MCU determines howto reconcile conflict to ensure safe operation.

In at least one embodiment, primary computer may be configured toprovide supervisory MCU with a confidence score, indicating primarycomputer's confidence in chosen result. In at least one embodiment, ifconfidence score exceeds a threshold, supervisory MCU may follow primarycomputer's direction, regardless of whether secondary computer providesa conflicting or inconsistent result. In at least one embodiment, whereconfidence score does not meet threshold, and where primary andsecondary computer indicate different results (e.g., a conflict),supervisory MCU may arbitrate between computers to determine appropriateoutcome.

In at least one embodiment, supervisory MCU may be configured to run aneural network(s) that is trained and configured to determine, based atleast in part on outputs from primary computer and secondary computer,conditions under which secondary computer provides false alarms. In atleast one embodiment, neural network(s) in supervisory MCU may learnwhen secondary computer's output may be trusted, and when it cannot. Forexample, in at least one embodiment, when secondary computer is aRADAR-based FCW system, a neural network(s) in supervisory MCU may learnwhen FCW system is identifying metallic objects that are not, in fact,hazards, such as a drainage grate or manhole cover that triggers analarm. In at least one embodiment, when secondary computer is acamera-based LDW system, a neural network in supervisory MCU may learnto override LDW when bicyclists or pedestrians are present and a lanedeparture is, in fact, safest maneuver. In at least one embodiment,supervisory MCU may include at least one of a DLA or GPU suitable forrunning neural network(s) with associated memory. In at least oneembodiment, supervisory MCU may comprise and/or be included as acomponent of SoC(s) 1604.

In at least one embodiment, ADAS system 1638 may include a secondarycomputer that performs ADAS functionality using traditional rules ofcomputer vision. In at least one embodiment, secondary computer may useclassic computer vision rules (if-then), and presence of a neuralnetwork(s) in supervisory MCU may improve reliability, safety andperformance. For example, in at least one embodiment, diverseimplementation and intentional non-identity makes overall system morefault-tolerant, especially to faults caused by software (orsoftware-hardware interface) functionality. For example, in at least oneembodiment, if there is a software bug or error in software running onprimary computer, and non-identical software code running on secondarycomputer provides same overall result, then supervisory MCU may havegreater confidence that overall result is correct, and bug in softwareor hardware on primary computer is not causing material error.

In at least one embodiment, output of ADAS system 1638 may be fed intoprimary computer's perception block and/or primary computer's dynamicdriving task block. For example, in at least one embodiment, if ADASsystem 1638 indicates a forward crash warning due to an objectimmediately ahead, perception block may use this information whenidentifying objects. In at least one embodiment, secondary computer mayhave its own neural network which is trained and thus reduces risk offalse positives, as described herein.

In at least one embodiment, vehicle 1600 may further includeinfotainment SoC 1630 (e.g., an in-vehicle infotainment system (IVI)).Although illustrated and described as an SoC, infotainment system 1630,in at least one embodiment, may not be an SoC, and may include, withoutlimitation, two or more discrete components. In at least one embodiment,infotainment SoC 1630 may include, without limitation, a combination ofhardware and software that may be used to provide audio (e.g., music, apersonal digital assistant, navigational instructions, news, radio,etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g.,hands-free calling), network connectivity (e.g., LTE, WiFi, etc.),and/or information services (e.g., navigation systems, rear-parkingassistance, a radio data system, vehicle related information such asfuel level, total distance covered, brake fuel level, oil level, dooropen/close, air filter information, etc.) to vehicle 1600. For example,infotainment SoC 1630 could include radios, disk players, navigationsystems, video players, USB and Bluetooth connectivity, carputers,in-car entertainment, WiFi, steering wheel audio controls, hands freevoice control, a heads-up display (“HUD”), HMI display 1634, atelematics device, a control panel (e.g., for controlling and/orinteracting with various components, features, and/or systems), and/orother components. In at least one embodiment, infotainment SoC 1630 mayfurther be used to provide information (e.g., visual and/or audible) touser(s) of vehicle, such as information from ADAS system 1638,autonomous driving information such as planned vehicle maneuvers,trajectories, surrounding environment information (e.g., intersectioninformation, vehicle information, road information, etc.), and/or otherinformation.

In at least one embodiment, infotainment SoC 1630 may include any amountand type of GPU functionality. In at least one embodiment, infotainmentSoC 1630 may communicate over bus 1602 (e.g., CAN bus, Ethernet, etc.)with other devices, systems, and/or components of vehicle 1600. In atleast one embodiment, infotainment SoC 1630 may be coupled to asupervisory MCU such that GPU of infotainment system may perform someself-driving functions in event that primary controller(s) 1636 (e.g.,primary and/or backup computers of vehicle 1600) fail. In at least oneembodiment, infotainment SoC 1630 may put vehicle 1600 into a chauffeurto safe stop mode, as described herein.

In at least one embodiment, vehicle 1600 may further include instrumentcluster 1632 (e.g., a digital dash, an electronic instrument cluster, adigital instrument panel, etc.). In at least one embodiment, instrumentcluster 1632 may include, without limitation, a controller and/orsupercomputer (e.g., a discrete controller or supercomputer). In atleast one embodiment, instrument cluster 1632 may include, withoutlimitation, any number and combination of a set of instrumentation suchas a speedometer, fuel level, oil pressure, tachometer, odometer, turnindicators, gearshift position indicator, seat belt warning light(s),parking-brake warning light(s), engine-malfunction light(s),supplemental restraint system (e.g., airbag) information, lightingcontrols, safety system controls, navigation information, etc. In someexamples, information may be displayed and/or shared among infotainmentSoC 1630 and instrument cluster 1632. In at least one embodiment,instrument cluster 1632 may be included as part of infotainment SoC1630, or vice versa.

Inference and/or training logic 715 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 715 are provided belowin conjunction with FIGS. 7A and/or 7B. In at least one embodiment,inference and/or training logic 715 may be used in system FIG. 16A forinferencing or predicting operations based, at least in part, on weightparameters calculated using neural network training operations, neuralnetwork functions and/or architectures, or neural network use casesdescribed herein.

FIG. 16B is a diagram of a system 1676 for communication betweencloud-based server(s) and autonomous vehicle 1600 of FIG. 16A, accordingto at least one embodiment. In at least one embodiment, system 1676 mayinclude, without limitation, server(s) 1678, network(s) 1690, and anynumber and type of vehicles, including vehicle 1600. In at least oneembodiment, server(s) 1678 may include, without limitation, a pluralityof GPUs 1684(A)-1684(H) (collectively referred to herein as GPUs 1684),PCIe switches 1682(A)-1682(D) (collectively referred to herein as PCIeswitches 1682), and/or CPUs 1680(A)-1680(B) (collectively referred toherein as CPUs 1680). GPUs 1684, CPUs 1680, and PCIe switches 1682 maybe interconnected with high-speed interconnects such as, for example andwithout limitation, NVLink interfaces 1688 developed by NVIDIA and/orPCIe connections 1686. In at least one embodiment, GPUs 1684 areconnected via an NVLink and/or NVSwitch SoC and GPUs 1684 and PCIeswitches 1682 are connected via PCIe interconnects. In at least oneembodiment, although eight GPUs 1684, two CPUs 1680, and four PCIeswitches 1682 are illustrated, this is not intended to be limiting. Inat least one embodiment, each of server(s) 1678 may include, withoutlimitation, any number of GPUs 1684, CPUs 1680, and/or PCIe switches1682, in any combination. For example, in at least one embodiment,server(s) 1678 could each include eight, sixteen, thirty-two, and/ormore GPUs 1684.

In at least one embodiment, server(s) 1678 may receive, over network(s)1690 and from vehicles, image data representative of images showingunexpected or changed road conditions, such as recently commencedroad-work. In at least one embodiment, server(s) 1678 may transmit, overnetwork(s) 1690 and to vehicles, neural networks 1692, updated neuralnetworks 1692, and/or map information 1694, including, withoutlimitation, information regarding traffic and road conditions. In atleast one embodiment, updates to map information 1694 may include,without limitation, updates for HID map 1622, such as informationregarding construction sites, potholes, detours, flooding, and/or otherobstructions. In at least one embodiment, neural networks 1692, updatedneural networks 1692, and/or map information 1694 may have resulted fromnew training and/or experiences represented in data received from anynumber of vehicles in environment, and/or based at least in part ontraining performed at a data center (e.g., using server(s) 1678 and/orother servers).

In at least one embodiment, server(s) 1678 may be used to train machinelearning models (e.g., neural networks) based at least in part ontraining data. In at least one embodiment, training data may begenerated by vehicles, and/or may be generated in a simulation (e.g.,using a game engine). In at least one embodiment, any amount of trainingdata is tagged (e.g., where associated neural network benefits fromsupervised learning) and/or undergoes other pre-processing. In at leastone embodiment, any amount of training data is not tagged and/orpre-processed (e.g., where associated neural network does not requiresupervised learning). In at least one embodiment, once machine learningmodels are trained, machine learning models may be used by vehicles(e.g., transmitted to vehicles over network(s) 1690, and/or machinelearning models may be used by server(s) 1678 to remotely monitorvehicles.

In at least one embodiment, server(s) 1678 may receive data fromvehicles and apply data to up-to-date real-time neural networks forreal-time intelligent inferencing. In at least one embodiment, server(s)1678 may include deep-learning supercomputers and/or dedicated AIcomputers powered by GPU(s) 1684, such as a DGX and DGX Station machinesdeveloped by NVIDIA. However, in at least one embodiment, server(s) 1678may include deep learning infrastructure that use CPU-powered datacenters.

In at least one embodiment, deep-learning infrastructure of server(s)1678 may be capable of fast, real-time inferencing, and may use thatcapability to evaluate and verify health of processors, software, and/orassociated hardware in vehicle 1600. For example, in at least oneembodiment, deep-learning infrastructure may receive periodic updatesfrom vehicle 1600, such as a sequence of images and/or objects thatvehicle 1600 has located in that sequence of images (e.g., via computervision and/or other machine learning object classification techniques).In at least one embodiment, deep-learning infrastructure may run its ownneural network to identify objects and compare them with objectsidentified by vehicle 1600 and, if results do not match anddeep-learning infrastructure concludes that AI in vehicle 1600 ismalfunctioning, then server(s) 1678 may transmit a signal to vehicle1600 instructing a fail-safe computer of vehicle 1600 to assume control,notify passengers, and complete a safe parking maneuver.

In at least one embodiment, server(s) 1678 may include GPU(s) 1684 andone or more programmable inference accelerators (e.g., NVIDIA's TensorRT3). In at least one embodiment, combination of GPU-powered servers andinference acceleration may make real-time responsiveness possible. In atleast one embodiment, such as where performance is less critical,servers powered by CPUs, FPGAs, and other processors may be used forinferencing. In at least one embodiment, inference and/or training logic715 are used to perform one or more embodiments. Details regardinginference and/or training logic 715 are provided below in conjunctionwith FIGS. 7A and/or 7B.

Other variations are within spirit of present disclosure. Thus, whiledisclosed techniques are susceptible to various modifications andalternative constructions, certain illustrated embodiments thereof areshown in drawings and have been described above in detail. It should beunderstood, however, that there is no intention to limit disclosure tospecific form or forms disclosed, but on contrary, intention is to coverall modifications, alternative constructions, and equivalents fallingwithin spirit and scope of disclosure, as defined in appended claims.

Use of terms “a” and “an” and “the” and similar referents in context ofdescribing disclosed embodiments (especially in context of followingclaims) are to be construed to cover both singular and plural, unlessotherwise indicated herein or clearly contradicted by context, and notas a definition of a term. Terms “comprising,” “having,” “including,”and “containing” are to be construed as open-ended terms (meaning“including, but not limited to,”) unless otherwise noted. Term“connected,” when unmodified and referring to physical connections, isto be construed as partly or wholly contained within, attached to, orjoined together, even if there is something intervening. Recitation ofranges of values herein are merely intended to serve as a shorthandmethod of referring individually to each separate value falling withinrange, unless otherwise indicated herein and each separate value isincorporated into specification as if it were individually recitedherein. Use of term “set” (e.g., “a set of items”) or “subset,” unlessotherwise noted or contradicted by context, is to be construed as anonempty collection comprising one or more members. Further, unlessotherwise noted or contradicted by context, term “subset” of acorresponding set does not necessarily denote a proper subset ofcorresponding set, but subset and corresponding set may be equal.

Conjunctive language, such as phrases of form “at least one of A, B, andC,” or “at least one of A, B and C,” unless specifically statedotherwise or otherwise clearly contradicted by context, is otherwiseunderstood with context as used in general to present that an item,term, etc., may be either A or B or C, or any nonempty subset of set ofA and B and C. For instance, in illustrative example of a set havingthree members, conjunctive phrases “at least one of A, B, and C” and “atleast one of A, B and C” refer to any of following sets: {A}, {B}, {C},{A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language isnot generally intended to imply that certain embodiments require atleast one of A, at least one of B, and at least one of C each to bepresent. In addition, unless otherwise noted or contradicted by context,term “plurality” indicates a state of being plural (e.g., “a pluralityof items” indicates multiple items). A plurality is at least two items,but can be more when so indicated either explicitly or by context.Further, unless stated otherwise or otherwise clear from context, phrase“based on” means “based at least in part on” and not “based solely on.”

Operations of processes described herein can be performed in anysuitable order unless otherwise indicated herein or otherwise clearlycontradicted by context. In at least one embodiment, a process such asthose processes described herein (or variations and/or combinationsthereof) is performed under control of one or more computer systemsconfigured with executable instructions and is implemented as code(e.g., executable instructions, one or more computer programs or one ormore applications) executing collectively on one or more processors, byhardware or combinations thereof. In at least one embodiment, code isstored on a computer-readable storage medium, for example, in form of acomputer program comprising a plurality of instructions executable byone or more processors. In at least one embodiment, a computer-readablestorage medium is a non-transitory computer-readable storage medium thatexcludes transitory signals (e.g., a propagating transient electric orelectromagnetic transmission) but includes non-transitory data storagecircuitry (e.g., buffers, cache, and queues) within transceivers oftransitory signals. In at least one embodiment, code (e.g., executablecode or source code) is stored on a set of one or more non-transitorycomputer-readable storage media having stored thereon executableinstructions (or other memory to store executable instructions) that,when executed (i.e., as a result of being executed) by one or moreprocessors of a computer system, cause computer system to performoperations described herein. A set of non-transitory computer-readablestorage media, in at least one embodiment, comprises multiplenon-transitory computer-readable storage media and one or more ofindividual non-transitory storage media of multiple non-transitorycomputer-readable storage media lack all of code while multiplenon-transitory computer-readable storage media collectively store all ofcode. In at least one embodiment, executable instructions are executedsuch that different instructions are executed by differentprocessors—for example, a non-transitory computer-readable storagemedium store instructions and a main central processing unit (“CPU”)executes some of instructions while a graphics processing unit (“GPU”)executes other instructions. In at least one embodiment, differentcomponents of a computer system have separate processors and differentprocessors execute different subsets of instructions.

Accordingly, in at least one embodiment, computer systems are configuredto implement one or more services that singly or collectively performoperations of processes described herein and such computer systems areconfigured with applicable hardware and/or software that enableperformance of operations. Further, a computer system that implements atleast one embodiment of present disclosure is a single device and, inanother embodiment, is a distributed computer system comprising multipledevices that operate differently such that distributed computer systemperforms operations described herein and such that a single device doesnot perform all operations.

Use of any and all examples, or exemplary language (e.g., “such as”)provided herein, is intended merely to better illuminate embodiments ofdisclosure and does not pose a limitation on scope of disclosure unlessotherwise claimed. No language in specification should be construed asindicating any non-claimed element as essential to practice ofdisclosure.

All references, including publications, patent applications, andpatents, cited herein are hereby incorporated by reference to sameextent as if each reference were individually and specifically indicatedto be incorporated by reference and were set forth in its entiretyherein.

In description and claims, terms “coupled” and “connected,” along withtheir derivatives, may be used. It should be understood that these termsmay be not intended as synonyms for each other. Rather, in particularexamples, “connected” or “coupled” may be used to indicate that two ormore elements are in direct or indirect physical or electrical contactwith each other. “Coupled” may also mean that two or more elements arenot in direct contact with each other, but yet still co-operate orinteract with each other.

Unless specifically stated otherwise, it may be appreciated thatthroughout specification terms such as “processing,” “computing,”“calculating,” “determining,” or like, refer to action and/or processesof a computer or computing system, or similar electronic computingdevice, that manipulate and/or transform data represented as physical,such as electronic, quantities within computing system's registersand/or memories into other data similarly represented as physicalquantities within computing system's memories, registers or other suchinformation storage, transmission or display devices.

In a similar manner, term “processor” may refer to any device or portionof a device that processes electronic data from registers and/or memoryand transform that electronic data into other electronic data that maybe stored in registers and/or memory. As non-limiting examples,“processor” may be a CPU or a GPU. A “computing platform” may compriseone or more processors. As used herein, “software” processes mayinclude, for example, software and/or hardware entities that performwork over time, such as tasks, threads, and intelligent agents. Also,each process may refer to multiple processes, for carrying outinstructions in sequence or in parallel, continuously or intermittently.Terms “system” and “method” are used herein interchangeably insofar assystem may embody one or more methods and methods may be considered asystem.

In present document, references may be made to obtaining, acquiring,receiving, or inputting analog or digital data into a subsystem,computer system, or computer-implemented machine. Obtaining, acquiring,receiving, or inputting analog and digital data can be accomplished in avariety of ways such as by receiving data as a parameter of a functioncall or a call to an application programming interface. In someimplementations, process of obtaining, acquiring, receiving, orinputting analog or digital data can be accomplished by transferringdata via a serial or parallel interface. In another implementation,process of obtaining, acquiring, receiving, or inputting analog ordigital data can be accomplished by transferring data via a computernetwork from providing entity to acquiring entity. References may alsobe made to providing, outputting, transmitting, sending, or presentinganalog or digital data. In various examples, process of providing,outputting, transmitting, sending, or presenting analog or digital datacan be accomplished by transferring data as an input or output parameterof a function call, a parameter of an application programming interfaceor interprocess communication mechanism.

Although discussion above sets forth example implementations ofdescribed techniques, other architectures may be used to implementdescribed functionality, and are intended to be within scope of thisdisclosure. Furthermore, although specific distributions ofresponsibilities are defined above for purposes of discussion, variousfunctions and responsibilities might be distributed and divided indifferent ways, depending on circumstances.

Furthermore, although subject matter has been described in languagespecific to structural features and/or methodological acts, it is to beunderstood that subject matter claimed in appended claims is notnecessarily limited to specific features or acts described. Rather,specific features and acts are disclosed as exemplary forms ofimplementing the claims.

What is claimed is:
 1. A computer-implemented method, comprising:determining importance values for one or more pixels of an image;generating, based at least in part on the importance values, a geometricmesh of the image corresponding to interaction probabilities for the oneor more pixels; importance sampling the geometric mesh using one or moresimulated light transport rays; determining, using the importancesampling, one or more pixel locations corresponding to interactionsbetween the one or more simulated light transport rays and the geometricmesh; and determining, based at least in part, on the importance values,a set of cumulative distribution functions (CDFs) for the one or morepixel locations, wherein the set of CDFs is determined based at least onprobability distributions of the importance values for at least one ofone or more individual rows or one or more individual columns of theimage.
 2. The computer-implemented method of claim 1, wherein the set ofCDFs is determined based at least on probability distributions of theimportance values for the one or more individual rows and the one ormore columns of the image.
 3. The computer-implemented method of claim1, wherein the importance sampling comprises a ray traversal search witha random number of simulated light transport rays.
 4. Thecomputer-implemented method of claim 1, further comprising: renderingthe image using, at least in part, a representation of illumination atthe one or more pixel locations associated with the interactions.
 5. Thecomputer-implemented method of claim 1, wherein the importance valuescorrespond to grayscale luminance values determined for the one or morepixels of the image.
 6. The computer-implemented method of claim 1,wherein the geometric mesh includes a series of triangulated ribbonscorresponding to rows or columns of the pixels.
 7. Thecomputer-implemented method of claim 1, wherein at least the determiningof the interactions is performed using hardware acceleration.
 8. Thecomputer-implemented method of claim 1, wherein the importance samplingcomprises Monte Carlo-based importance sampling, the Monte Carlo-basedimportance sampling comprising a probability distribution functionderived based, at least on one or more partial derivatives of thegeometric mesh at one or more of the intersection points.
 9. A system,comprising: one or more processing units to: determine importance valuesfor one or more pixels of an image; generate, based at least in part onthe importance values, a geometric mesh of the image corresponding tointeraction probabilities for the one or more pixels; importance samplethe geometric mesh using one or more simulated light transport rays;determine, using the importance sample, one or more pixel locationscorresponding to interactions between the one or more simulated lighttransport rays and the geometric mesh; and determine, based at least onthe importance values, a set of cumulative distribution functions (CDFs)for the one or more pixel locations wherein the set of CDFs isdetermined based at least on probability distributions of the importancevalues for at least one of one or more individual rows or one or moreindividual columns of the image.
 10. The system of claim 9, wherein thesystem is comprised in at least one of: a system for performingsimulation operations; a system for performing simulation operations totest or validate autonomous machine applications; a system for renderinggraphical output; a system for performing deep learning operations; asystem implemented using an edge device; a system incorporating one ormore Virtual Machines (VMs); a system implemented at least partially ina data center; or a system implemented at least partially using cloudcomputing resources.
 11. The system of claim 9, wherein the importancevalues correspond to grayscale luminance values determined for therespective pixels of the image.
 12. The system of claim 9, wherein theset of CDFs is determined based at on probability distributions of theimportance values for the one or more individual rows and the one ormore individual columns of the image.
 13. The system of claim 9, whereinat least the determining of the interactions is performed using hardwareacceleration.
 14. The system of claim 9, wherein the one or moreprocessing units are further to render the image using, at least inpart, a representation of illumination at the one or more pixellocations associated with the interactions.
 15. A processor, comprising:one or more processing units to determine interactions between one ormore simulated light transport rays and one or more pixel locations of ageometric mesh, geometric mesh corresponding to interactionprobabilities for the one or more pixel locations based at on importancevalues corresponding to respective pixel locations of the one or morepixel locations, and to determine based at least on the importancevalues, a set of cumulative distribution functions (CDFs) for the one ormore pixel locations, wherein the set of CDFs is determined based atleast on probability distributions of the importance values for at leastone of one or more individual rows or one or more individual columns ofthe image.
 16. The processor of claim 15, wherein the processor iscomprised in at least one of: a system for performing simulationoperations; a system for performing simulation operations to test orvalidate autonomous machine applications; a system for renderinggraphical output; a system for performing deep learning operations; asystem implemented using an edge device; a system incorporating one ormore Virtual Machines (VMs); a system implemented at least partially ina data center; or a system implemented at least partially using cloudcomputing resources.
 17. The processor of claim 15, wherein the set ofCDFs is determined based at least on probability distributions of theimportance values for the one or more individual rows and the one ormore individual columns of the image.